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FDC37N769 参数 Datasheet PDF下载

FDC37N769图片预览
型号: FDC37N769
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V超级I / O控制器具有红外支持针对便携式应用 [3.3V SUPER I/O CONTROLLER WITH INFRARED SUPPORT FOR PORTABLE APPLICATIONS]
分类和应用: 控制器便携式
文件页数/大小: 138 页 / 713 K
品牌: SMSC [ SMSC CORPORATION ]
 浏览型号FDC37N769的Datasheet PDF文件第16页浏览型号FDC37N769的Datasheet PDF文件第17页浏览型号FDC37N769的Datasheet PDF文件第18页浏览型号FDC37N769的Datasheet PDF文件第19页浏览型号FDC37N769的Datasheet PDF文件第21页浏览型号FDC37N769的Datasheet PDF文件第22页浏览型号FDC37N769的Datasheet PDF文件第23页浏览型号FDC37N769的Datasheet PDF文件第24页  
RESET  
N/A  
1
1
0
0
0
1
1
CONDITION  
nDRIVE SELECT 2, Bit 0  
Active low status of the DS2 disk interface output.  
nDRIVE SELECT 3, Bit 1  
Active low status of the DS3 disk interface output.  
Write Gate, Bit 2  
Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is  
cleared by the read of the DIR register.  
Read Data, Bit 3  
Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is  
cleared by the read of the DIR register.  
Write Data, Bit 4  
Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and  
is cleared by the read of the DIR register. This bit is not gated with WGATE.  
nDRIVE SELECT 0, Bit 5  
Active low status of the DS0 disk interface output.  
nDRIVE SELECT 1, Bit 6  
Active low status of the DS1 disk interface output.  
nDRV2, Bit 7  
Active low status of the DRV2 disk interface input.  
DIGITAL OUTPUT REGISTER (DOR)  
The Digital Output register (Base Address + 2) controls the drive select and motor enables of the disk interface  
outputs (Table 9 and Table 10). The DOR also contains the DMA logic enable and a software reset bit. The DOR is  
read/write and unaffected by a software reset.  
Table 9 - Digital Output Register  
7
6
5
4
3
2
1
0
MOT EN3 MOT EN2 MOT EN1 MOT EN0 DMAEN nRESET DRIVE  
DRIVE  
SEL1  
SEL0  
RESET  
0
0
0
0
0
0
0
0
CONDITION  
DOR Bit Descriptions  
DRIVE SELECT, Bits 0 - 1  
These two bits are binary encoded for the four drive selects DS0-DS3, thereby allowing only one drive to be selected  
at one time.  
nRESET, Bit 2  
A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic “1” is written to  
this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR  
register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this  
register is a valid method of issuing a software reset.  
SMSC DS – FDC37N769  
Page 20 of 137  
Rev. 12/21/2000  
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