Track, Bit 4
Active high status of the TRK0 disk interface input.
Step, Bit 5
Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active,
and is cleared with a read from the DIR register, or with a hardware or software reset.
DMA Request, Bit 6
Active high status of the DRQ output pin. Interrupt Pending, Bit 7 Active high bit indicating the state of the Floppy
Disk Interrupt output.
STATUS REGISTER B (SRB)
Status Register B (Base Address + 1) is read-only and monitors the state of several disk interface pins in PS/2
interface mode (Table 7) and Model 30 interface mode (Table 8). SRB can be accessed at any time when in these
modes. During a read in PC/AT interface mode the data bus pins D0 - D7 are held in a high impedance state.
PS/2 Interface Mode
Table 7 - SRB PS/2 Mode
7
1
6
1
5
4
3
2
1
0
DRIVE
WDATA
RDATA
WGATE
MOT
MOT
SEL0
TOGGLE TOGGLE
EN1
EN0
RESET
1
1
0
0
0
0
0
0
CONDITION
Motor Enable 0, Bit 0
Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a
software reset.
Motor Enable 1, Bit 1
Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a
software reset.
Write Gate, Bit 2
Active high status of the WGATE disk interface output.
Read Data Toggle, Bit 3
Every inactive edge of the RDATA input causes this bit to change state.
Write Data Toggle, Bit 4
Every inactive edge of the WDATA input causes this bit to change state.
Drive Select 0, Bit 5
Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset,
it is unaffected by a software reset.
Reserved, Bits 6 - 7
Always read as a logic “1”.
PS/2 Model 30 Interface Mode
Table 8 - SRB PS/2 Model 30 Mode
7
6
5
4
3
2
1
0
nDRV2
nDS1
nDS0
WDATA RDATA F/F WGATE
nDS3
nDS2
F/F
F/F
SMSC DS – FDC37N769
Page 19 of 137
Rev. 12/21/2000
SMSC [ SMSC CORPORATION ]
