EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of which are listed below. The individual features are explained in
greater detail in the remainder of this section.
High performance half-duplex forward and reverse channel
Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
Vocabulary
The following terms are used in this document:
assert
When
state.
a
signal asserts it transitions to a “true” state, when a signal deasserts it transitions to a “false”
forward Host to Peripheral communication.
reverse Peripheral to Host communication.
Pword A port word; equal in size to the width of the ISA interface. For this implementation, PWord is always 8
bits.
1
0
A high level
A low level
These terms may be considered synonymous:
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
Reference Document:
IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.09, Jan 7, 1993. This document is
available from Microsoft. The bit map of the Extended Parallel Port registers is shown in Table 65.
Table 65 - ECP Registers
D7
PD7
D6
D5
D4
D3
D2
D1
D0
data
PD6
PD5
PD4
PD3
PD2
PD1
PD0
ecpAFifo2
dsr1
dcr1
Addr/RLE
nBusy
0
Address or RLE field
nAck
0
PError
Select
nFault
0
0
0
Direction
ackIntEn
SelectIn
nInit
autofd strob
e
cFifo2
ecpDFifo2
tFifo2
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
cnfgA
cnfgB
ecr
0
0
0
0
1
0
0
0
0
0
0
0
0
compress
intrValue
MODE
0
nErrIntrEn
dmaEn
serviceIntr
full
empt
y
Note1
Note2
These registers are available in all modes.
All FIFOs use one common 16 byte FIFO.
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