EXTENDED CAPABILITIES PARALLEL PORT
A port word; equal in size to the
width of the ISA interface. For this
implementation, PWord is always 8
bits.
A high level.
A low level.
PWord
ECP provides a number of advantages, some of
which are listed below. The individual features
are explained in greater detail in the remainder
of this section.
1
0
High performance half-duplex forward and
reverse channel
Interlocked handshake, for fast reliable
transfer
Optional single byte RLE compression for
improved throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
·
·
·
These terms may be considered synonymous:
PeriphClk, nAck
·
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
·
·
·
·
·
·
·
·
·
·
·
·
·
ECPMode, nSelectln
HostClk, nStrobe
Reference Document:
Vocabulary
The following terms are used in this document:
IEEE 1284 Extended Capabilities Port Protocol
and ISA Interface Standard, Rev 1.09, Jan 7,
When
a
signal
asserts it
assert
transitions to a "true" state, when a
signal deasserts it transitions to a
"false" state.
1993.
Microsoft.
This document is available from
Host to Peripheral communication.
Peripheral to Host communication.
The bit map of the Extended Parallel Port
registers is:
forward
reverse
D7
D6
D5
D4
D3
D2
D1
D0
Note
data
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
ecpAFifo Addr/RL
E
Address or RLE field
2
dsr
nBusy
0
nAck
0
PError
Select
nFault
0
0
0
1
1
2
2
2
Direction
dcr
ackIntEn SelectIn
nInit
autofd strobe
cFifo
ecpDFifo
tFifo
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
cnfgA
cnfgB
ecr
0
0
0
0
1
0
0
0
0
0
0
0
0
0
compress intrValue
MODE
nErrIntrEn
serviceIntr
dmaEn
full
empty
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
96
SMSC [ SMSC CORPORATION ]
