Data or Address cycle. IOCHRDY is driven
active low when nWAIT is active low during the
EPP cycle. This can be used to extend the cycle
EPP 1.7 Read
The timing for a read operation (data) is shown
in timing diagram EPP 1.7 Read Data cycle.
IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle
can complete when nWAIT is inactive high.
time.
The write cycle can complete when
nWAIT is inactive high.
Write Sequence of Operation
1. The host sets PDIR bit in the control
register to
nWRITE.
a
logic "0".
This asserts
Read Sequence of Operation
2. The host selects an EPP register, places
data on the SData bus and drives nIOW
active.
3. The chip places address or data on PData
bus.
1. The host sets PDIR bit in the control
register to a logic "1". This deasserts
nWRITE and tri-states the PData bus.
2. The host selects an EPP register and drives
nIOR active.
4. Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
5. If nWAIT is asserted, IOCHRDY is
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
3. Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
4. If nWAIT is asserted, IOCHRDY is
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
6. When the host deasserts nI0W the chip
deasserts nDATASTB or nADDRSTRB and
latches the data from the SData bus for the
PData bus.
7. Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
5. The Peripheral drives PData bus valid.
6. The Peripheral deasserts nWAIT,
indicating that PData is valid and the chip
may begin the termination phase of the
cycle.
7. When the host deasserts nI0R the chip
deasserts nDATASTB or nADDRSTRB.
8. Peripheral tri-states the PData bus.
9. Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
94
SMSC [ SMSC CORPORATION ]
