checked (receive data) between the last data
word bit and the first stop bit of the serial data.
(The parity bit is used to generate an even or
odd number of 1s when the data word bits and
the parity bit are summed).
LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
This register contains the format information of
the serial line. The bit definitions are:
Bits 0 and 1
Bit 4
These two bits specify the number of bits in
each transmitted or received serial character.
The encoding of bits 0 and 1 is as follows:
Even Parity Select bit. When bit 3 is a logic "1"
and bit 4 is a logic "0", an odd number of logic
"1"'s is transmitted or checked in the data word
bits and the parity bit. When bit 3 is a logic "1"
and bit 4 is a logic "1" an even number of bits is
transmitted and checked.
BIT 1 BIT 0 WORD LENGTH
0
0
1
1
0
1
0
1
5 Bits
6 Bits
7 Bits
8 Bits
Bit 5
Stick Parity bit. When bit 3 is a logic "1" and bit
5 is a logic "1", the parity bit is transmitted and
then detected by the receiver in the opposite
state indicated by bit 4.
The Start, Stop and Parity bits are not included
in the word length.
Bit 6
Set Break Control bit. When bit 6 is a logic "1",
the transmit data output (TXD) is forced to the
Spacing or logic "0" state and remains there
(until reset by a low level bit 6) regardless of
other transmitter activity. This feature enables
Bit 2
This bit specifies the number of stop bits in each
transmitted or received serial character. The
following table summarizes the information.
the Serial Port to alert
communications system.
a terminal in a
NUMBER OF
STOP BITS
BIT 2 WORD LENGTH
0
1
1
1
1
--
1
1.5
2
Bit 7
Divisor Latch Access bit (DLAB). It must be set
high (logic "1") to access the Divisor Latches of
the Baud Rate Generator during read or write
operations. It must be set low (logic "0") to
access the Receiver Buffer Register, the
Transmitter Holding Register, or the Interrupt
Enable Register.
5 bits
6 bits
7 bits
8 bits
2
2
Note: The receiver will ignore all stop bits
beyond the first, regardless of the number used
in transmitting.
MODEM CONTROL REGISTER (MCR)
Address Offset
=
4H, DLAB
=
X,
READ/WRITE
Bit 3
This 8 bit register controls the interface with the
MODEM or data set (or device emulating a
MODEM). The contents of the MODEM control
register are described below.
Parity Enable bit. When bit 3 is a logic "1", a
parity bit is generated (transmit data) or
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