Table 35 - Register Summary for an Individual UART Channel
REGISTER
ADDRESS*
REGISTER
SYMBOL
REGISTER NAME
BIT 0
BIT 1
ADDR = 0
DLAB = 0
Receive Buffer Register (Read Only)
RBR
THR
IER
Data Bit 0
(Note 1)
Data Bit 1
ADDR = 0
DLAB = 0
Transmitter Holding Register (Write
Only)
Data Bit 0
Data Bit 1
ADDR = 1
DLAB = 0
Interrupt Enable Register
Enable
Received
Data
Enable
Transmitter
Holding
Available
Interrupt
(ERDAI)
Register
Empty
Interrupt
(ETHREI)
ADDR = 2
ADDR = 2
ADDR = 3
Interrupt Ident. Register (Read Only)
FIFO Control Register (Write Only)
Line Control Register
IIR
"0" if Interrupt Interrupt ID
Pending Bit
FCR
LCR
FIFO Enable RCVR FIFO
Reset
Word Length
Select Bit 0
(WLS0)
Word Length
Select Bit 1
(WLS1)
ADDR = 4
MODEM Control Register
MCR
Data
Terminal
Ready (DTR)
Request to
Send (RTS)
Data Ready
(DR)
ADDR = 5
ADDR = 6
Line Status Register
LSR
Overrun Error
(OE)
Delta Clear to
Send (DCTS)
MODEM Status Register
MSR
Delta Data
Set Ready
(DDSR)
ADDR = 7
Scratch Register (Note 4)
Divisor Latch (LS)
SCR
DDL
Bit 0
Bit 0
Bit 1
Bit 1
ADDR = 0
DLAB = 1
ADDR = 1
DLAB = 1
Divisor Latch (MS)
DLM
Bit 8
Bit 9
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
83
SMSC [ SMSC CORPORATION ]
