XMITTER are controlled separately, either one or both
can be in the polled mode of operation.
mode, the IIR is not affected since EIR bit 2=0.
Bit 5 indicates when the XMIT FIFO is empty.
Bit 6 indicates that both the XMIT FIFO and shift
register are empty.
Bit 7 indicates whether there are any errors in the
RCVR FIFO.
-
-
In this mode, the user's program will check RCVR and
XMITTER status via the LSR. LSR definitions for the
FIFO Polled Mode are as follows:
-
-
-
Bit 0=1 as long as there is one byte in the RCVR
FIFO.
Bits 1 to 4 specify which error(s) have occurred.
Character error status is handled the same way as
when in the interrupt
There is no trigger level reached or timeout condition
indicated in the FIFO Polled Mode, however, the RCVR
and XMIT FIFOs are still fully capable of holding
characters.
Table 33 - Baud Rates Using 1.8462 MHz Clock (24 MHz/13)
DESIRED
DIVISOR USED TO
GENERATE 16X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL*
CROC:
BAUD RATE
BIT 7 OR 6
50
75
2307
1538
1049
858
769
384
192
96
0.03
0.03
0.005
0.01
0.03
0.16
0.16
0.16
0.16
0.5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
230400
460800
64
58
48
0.16
0.16
0.16
0.16
0.16
0.16
0.16
1.6
32
24
16
12
6
3
2
1
0.16
0.16
0.16
32770
32769
1
81
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