PARALLEL PORT
The FDC37C669 incorporates an
IBM XT/AT
The FDC37C669 also incorporates SMSC's ChiProtect
circuitry, which prevents possible damage to the parallel
port due to printer power-up.
compatible parallel port. The FDC37C669 supports the
optional PS/2 type bi-directional parallel port (SPP), the
Enhanced Parallel Port (EPP) and the Extended
Capabilities Port (ECP) parallel port modes. Refer to the
FDC37C669 Configuration Registers and FDC37C669
Hardware Configuration description for information on
disabling, power down, changing the base address of the
parallel port, and selecting the mode of operation.
The functionality of the Parallel Port is achieved through
the use of eight addressable ports, with their
associated registers and control gating. The control and
data port are read/write by the CPU, the status port is
read/write in the EPP mode. The address map of the
Parallel Port is shown below:
DATA PORT
BASE ADDRESS + 00H
BASE ADDRESS + 01H
BASE ADDRESS + 02H
BASE ADDRESS + 03H
EPP DATA PORT 0
EPP DATA PORT 1
EPP DATA PORT 2
EPP DATA PORT 3
BASE ADDRESS + 04H
BASE ADDRESS + 05H
BASE ADDRESS + 06H
BASE ADDRESS + 07H
STATUS PORT
CONTROL PORT
EPP ADDR PORT
The bit map of these registers is:
D0
D1
PD1
0
D2
PD2
0
D3
D4
D5
PD5
PE
D6
D7
Note
DATA PORT
PD0
PD3
PD4
SLCT
PD6
PD7
1
1
STATUS
PORT
TMOUT
nERR
nACK nBUSY
CONTROL
PORT
STROBE AUTOFD nINIT
SLC
PD3
PD3
PD3
PD3
PD3
IRQE
PD4
PD4
PD4
PD4
PD4
PCD
PD5
PD5
PD5
PD5
PD5
0
0
1
EPP ADDR
PORT
PD0
PD0
PD0
PD0
PD0
PD1
PD1
PD1
PD1
PD1
PD2
PD2
PD2
PD2
PD2
PD6
PD6
PD6
PD6
PD6
AD7
PD7
PD7
PD7
PD7
2,3
2,3
2,3
2,3
2,3
EPP DATA
PORT 0
EPP DATA
PORT 1
EPP DATA
PORT 2
EPP DATA
PORT 3
Note 1: These registers are available in all modes.
Note 2: These registers are only available in EPP mode.
Note 3: For EPP mode, IOCHRDY must be connected to the ISA bus.
87
SMSC [ SMSC CORPORATION ]
