Bit 0
This feature allows the processor to verify the transmit
and receive data paths of the Serial Port. In the
diagnostic mode, the receiver and the transmitter
interrupts are fully operational. The MODEM Control
Interrupts are also operational but the interrupts' sources
are now the lower four bits of the MODEM Control
Register instead of the MODEM Control inputs. The
interrupts are still controlled by the Interrupt Enable
Register.
This bit controls the Data Terminal Ready (nDTR) output.
When bit 0 is set to a logic "1", the nDTR output is
forced to a logic "0". When bit 0 is a logic "0", the nDTR
output is forced to a logic "1".
Bit 1
This bit controls the Request To Send (nRTS) output. Bit
1 affects the nRTS output in a manner identical to that
described above for bit 0.
Bits 5 through 7
Bit 2
These bits are permanently set to logic zero.
This bit controls the Output 1 (OUT1) bit. This bit does
not have an output pin and can only be read or written by
the CPU.
LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
Bit 0
Bit 3
Data Ready (DR). It is set to a logic "1" whenever a
complete incoming character has been received and
transferred into the Receiver Buffer Register or the FIFO.
Bit 0 is reset to a logic "0" by reading all of the data in the
Receive Buffer Register or the FIFO.
Output 2 (OUT2). This bit is used to enable an UART
interrupt. When OUT2 is a logic "0", the serial port
interrupt output is forced to a high impedance state -
disabled. When OUT2 is a logic "1", the serial port
interrupt outputs are enabled.
Bit 1
Bit 4
Overrun Error (OE). Bit 1 indicates that data in the
Receiver Buffer Register was not read before the next
character was transferred into the register, thereby
destroying the previous character. In FIFO mode, an
overrunn error will occur only when the FIFO is full and
the next character has been completely received in the
shift register, the character in the shift register is
overwritten but not transferred to the FIFO. The OE
indicator is set to a logic "1" immediately upon detection
of an overrun condition, and reset whenever the Line
Status Register is read.
This bit provides the loopback feature for diagnostic
testing of the Serial Port. When bit 4 is set to logic "1",
the following occur:
1. The TXD is set to the Marking State(logic "1").
2. The receiver Serial Input (RXD) is disconnected.
3. The output of the Transmitter Shift Register is "looped
back" into the Receiver Shift Register input.
4. All MODEM Control inputs (nCTS, nDSR, nRI and
nDCD) are disconnected.
5. The four MODEM Control outputs (nDTR, nRTS,
OUT1 and OUT2) are internally connected to the
four MODEM Control inputs (nDSR, nCTS, RI and
DCD) respectively.
Bit 2
Parity Error (PE). Bit 2 indicates that the received data
character does not have the correct even or odd parity, as
selected by the even parity select bit. The PE is set to a
logic "1" upon detection of a parity error and is reset to a
logic "0" whenever the Line Status Register is read. In
the FIFO mode this error is associated with the particular
character in the FIFO it applies to. This error is indicated
when the associated character is at the top of the FIFO.
6. The Modem Control output pins are forced inactive
high.
7. Data that is transmitted is immediately received.
Bit 3
Framing Error (FE). Bit 3 indicates that the received
character did not have a valid stop bit. Bit 3 is set to a
logic "1" whenever the stop bit following the last data bit
77
SMSC [ SMSC CORPORATION ]
