GPIO CONFIGURATION
Each GPIO port has an 8-bit configuration register
The state of the GPIO polarity bit[1], except for the
that controls the behavior of the pin. The GPIO
configuration registers are only accessible when
the FDC37B78x is in the Configuration state; more
information can be found in the Configuration
section of this specification.
EETI function.
The interrupt channel for the group Interrupts is
selected by the GP_INT[2:1] configuration
registers defined in the FDC37B78x Configuration
Register Section. The group interrupts are the
"ORed" function of the group interrupt enabled
GPIO ports and will represent a standard ISA
interrupt (edge high). GPIO Group 1 and 2
Interrupts can generate SMI events, wake-up
events through the Soft Power Management logic,
and SCI/PME events. See the ACPI, PME and
SMI section for details. When the group interrupt is
enabled on a GPIO input port, the interrupt
circuitry contains a selectable digital debounce
filter so that switches or push-buttons may be
directly connected to the chip. The debounce
filters reject signals with pulse widths ≤1ms and
are enabled per interrupt group in the GP_INT[2:1]
configuration registers.
Each GPIO port may be configured as either an
input or an output. If the pin is configured as an
output, it can be programmed as open-drain or
push-pull. Inputs and outputs can be configured
as non-inverting or inverting and can be
programmed to generate an interrupt. GPIO ports
can also be configured as a pre-defined alternate
function.
Bit[0] of each GPIO Configuration
Register determines the port direction, bit[1]
determines the signal polarity, bits[4:3] select the
port function, bit[5] enables the interrupt, and bit[7]
determines the output driver type select. The
GPIO configuration register Output Type select
bit[7] applies to GPIO functions, the Watchdog
Timer WDT, the LED and the nSMI Alternate
functions. The basic GPIO configuration options
are summarized in TABLE 55. For Alternate
functions, the pin direction is set and controlled
internally, regardless of the state of the GPIO
Direction bit[0]. Also, selected Alternate INPUT
functions cannot be inverted, regardless of
The state of unconnected GPIO alternate input
functions is inactive. For example, if bits[4:3] in
LD8 -CRCB are not “00”, i.e. nROMCS is not the
selected function for GP53, internally the state of
nROMCS is inactive, “1”.
126
SMSC [ SMSC CORPORATION ]
