followed. This could cause a system fault. The
host interrupt controller is responsible for
ensuring that these latency issues are mitigated.
The recommended solution is to delay EOIs and
ISR Reads to the interrupt controller by the same
amount as the IRQSER Cycle latency in order to
ensure that these events do not occur out of
order.
Stop Cycle Control
Once all IRQ/Data Frames have completed the
Host Controller will terminate IRQSER activity by
initiating a Stop Frame. Only the Host Controller
can initiate the Stop Frame. A Stop Frame is
indicated when the IRQSER is low for two or
three clocks. If the Stop Frame’s low time is two
clocks then the next IRQSER Cycle’s sampled
mode is the Quiet mode; and any IRQSER
device may initiate a Start Frame in the second
clock or more after the rising edge of the Stop
Frame’s pulse. If the Stop Frame’s low time is
three clocks then the next IRQSER Cycle’s
sampled mode is the Continuos mode; and only
the Host Controller may initiate a Start Frame in
the second clock or more after the rising edge of
the Stop Frame’s pulse.
AC/DC Specification Issue
All IRQSER agents must drive / sample IRQSER
synchronously related to the rising edge of PCI
bus clock. IRQSER (SIRQ) pin uses the
electrical specification of PCI bus. Electrical
parameters will follow PCI spec. section 4,
sustained tri-state.
Reset and Initialization
Latency
The IRQSER bus uses RESET_DRV as its reset
signal. The IRQSER pin is tri-stated by all agents
while RESET_DRV is active. With reset,
IRQSER Slaves are put into the (continuous)
IDLE mode. The Host Controller is responsible
for starting the initial IRQSER Cycle to collect
system’s IRQ/Data default values. The system
then follows with the Continuous/Quiet mode
protocol (Stop Frame pulse width) for
subsequent IRQSER Cycles. It is Host
Controller’s responsibility to provide the default
values to 8259’s and other system logic before
Latency for IRQ/Data updates over the IRQSER
bus in bridge-less systems with the minimum
IRQ/Data Frames of seventeen, will range up to
96 clocks (3.84μS with a 25MHz PCI Bus or
2.88uS with a 33MHz PCI Bus). If one or more
PCI to PCI Bridge is added to a system, the
latency for IRQ/Data updates from the secondary
or tertiary buses will be a few clocks longer for
synchronous buses, and approximately double
for asynchronous buses.
the first IRQSER Cycle is performed.
For
EOI/ISR Read Latency
IRQSER system suspend, insertion, or removal
application, the Host controller should be
programmed into Continuous (IDLE) mode first.
This is to guarantee IRQSER bus is in IDLE state
before the system configuration changes.
Any serialized IRQ scheme has a potential
implementation issue related to IRQ latency. IRQ
latency could cause an EOI or ISR Read to
precede an IRQ transition that it should have
BIOS BUFFER
The chip contains one 245 type buffer that can be
used for a BIOS Buffer. If the BIOS buffer is not
used, then nROMCS must be tied high or pulled
up to Vcc with a resistor so as not to interfere with
transmission from the RD bus to the SD bus or
from the SD bus to the RD bus. The direction of
the transfer is controlled by nROMOE. The enable
input, nROMCS, can be used to disable the
transfer and isolate the buses.
the boot ROM.
This function allows data
nROMCS
nROMOE
DESCRIPTION
RD[0:7] data to SD[0:7] bus
SD[0:7] data to RD[0:7]
Isolation
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