GENERAL PURPOSE I/O
and an 8-bit configuration control register. The
data register for each GPIO port is represented as
a bit in one of three 8-bit GPIO DATA Registers,
GP1, GP5, and GP6. All of the GPIO registers are
located in Logical Device Block No. 8 in the
FDC37B78x device configuration space. The
GPIO DATA Registers are also optionally
available at different addresses when the
FDC37B78x is in the Run state. The GPIO ports
with their alternate functions and configuration
state register addresses are listed in. Note: three
bits 5-7 of GP5 are not implemented.
The FDC37B78x provides
a set of flexible
Input/Output control functions to the system
designer through the 21 dedicated independently
programmable General Purpose I/O pins (GPIO).
The GPIO pins can perform simple I/O or can be
individually configured to provide predefined
alternate functions.
VBAT Power-On-Reset
configures all GPIO pins as non-inverting inputs.
Description
Each GPIO port requires a 1-bit data register
TABLE 52 - GENERAL PURPOSE I/O PORT ASSIGNMENTS
DATA
DATA
REGISTER
BIT NO.
CONFIG.
REGISTER4
(HEX)
CRE0
CRE1
CRE2
CRE3
CRE4
CRE5
CRE6
CRE7
CRC8
CRCA
CRCB
CRCC
CRD0
CRD1
CRD2
CRD3
CRD4
CRD5
CRD6
CRD7
PIN NO.
QFP
77
78
79
80
81
82
4
DEFAULT
FUNCTION
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
ALT.
FUNC. 1
nSMI
nRING
WDT
ALT.
FUNC. 2
ALT.
FUNC. 3
REGISTER
4 (HEX)
GP1
-
-
-
0
1
2
3
4
5
6
7
0
2
3
4
0
1
2
3
4
5
6
7
EETI1
P17
-
(CRF6)
EETI1
LED
-
-
-
-
-
-
IRRX2
IRTX2
nMTR1
nDS1
IRQ14
GPIO
IRQ11
IRQ12
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
-
-
-
-
6
39
2
GPIO
PCI_CLK
DRVDEN15
nROMCS2
nROMOE2
RD02,3
GPIO
IRQ8
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GP5
(CRF9)
nSMI
EETI1
EETI1
nSMI
LED
nRING
WDT
P17
-
91
92
83
84
85
86
87
88
89
90
GP6
(CRFA)
RD12,3
RD22,3
RD32,3
RD42,3
RD52,3
IRQ7
IRQ8
IRQ10
RD62,3
-
-
RD72,3
Note 1. Refer to the section on Either Edge Triggered Interrupt Inputs.
Note 2. At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for
alternate functions, nROMCS must stay high until those pins are finished being programmed.
Note 3. These pins cannot be programmed as open drain pins in their original function.
Note 4. The GPIO Data and Configuration Registers are located in Logical Device 8.
Note 5: This pin defaults to its GPIO function. See Configuration Registers.
when the chip is in the run state if CR03 Bit[7] = 1.
The host uses an Index and Data port to access
these registers. The Index and Data port power-
on default addresses are 0xEA and 0xEB
respectively. In the configuration state the Index
RUN STATE GPIO DATA REGISTER ACCESS
The GPIO data registers as well as the Watchdog
Timer Control, and the Soft Power Enable and
Status registers can be accessed by the host
123
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