Notes: HARD RESET: RESET_DRV pin asserted
SOFT RESET: Bit 0 of Configuration Control register set to one
All host accesses are blocked for 500µs after Vcc POR (see Power-up Timing Diagram)
Table 52 – FDC37B77x Configuration Registers Summary
HARD
RESET
VCC
POR
SOFT
RESET
VTR
POR
INDEX
TYPE
CONFIGURATION REGISTER
GLOBAL CONFIGURATION REGISTERS
0x02
0x03
0x07
0x20
0x21
0x22
0x23
W
R/W
R/W
R
0x00
0x03
0x00
0x00
0x03
0x00
-
-
0x00
0x03
0x00
Configuration Control
Index Address
0x00
Logical Device Number
Device ID - hard wired
Device Rev - hard wired
Power Control3
0x43
Current Revision
R
R/W
R/W
0x00
0x00
0x00
0x00
0x00
-
0x00
0x00
POWER MGMT
0x24
0x26
R/W
R/W
0x04
0x04
-
-
0x04
-
OSC
Sysop
Sysop
Configuration Port Address Byte 0
=0: 0xF0 =0: 0xF0
Sysop Sysop
=1: 0x70 =1: 0x70
Sysop Sysop
=0: 0x03 =0: 0x03
Sysop Sysop
=1: 0x03 =1: 0x03
0x27
R/W
-
-
Configuration Port Address Byte 1
0x2B
0x2C
0x2D
0x2E
0x2F
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
0x00
0x00
0x00
0x00
0x00
-
-
-
-
-
0x00
0x00
0x00
0x00
0x00
TEST 4
TEST 5
TEST 1
TEST 2
TEST 3
LOGICAL DEVICE 0 CONFIGURATION REGISTERS (FDD)
0x30
0x60,
0x61
0x70
0x74
R/W
R/W
0x00
0x03,
0xF0
0x06
0x02
0x00
0x03,
0xF0
0x06
0x02
0x00
0x03,
0xF0
0x06
0x02
0x00
0x03,
0xF0
0x06
0x02
Activate
Primary Base I/O Address
R/W
R/W
Primary Interrupt Select
DMA Channel Select
133
SMSC [ SMSC CORPORATION ]
