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FDC37B72X_07 参数 Datasheet PDF下载

FDC37B72X_07图片预览
型号: FDC37B72X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 128引脚增强型超级I / O控制器,支持ACPI [128 Pin Enhanced Super I/O Controller with ACPI Support]
分类和应用: 控制器
文件页数/大小: 238 页 / 816 K
品牌: SMSC [ SMSC CORPORATION ]
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Auxiliary I/O, Logical Device 8  
Table 73 - Auxiliary I/O, Logical Device 8 [Logical Device Number = 0x08]  
NAME  
Soft Power Enable  
Register 1  
REG INDEX  
0xB0 R/W  
DEFINITION  
STATE  
The following bits are the enables for the wake-up  
function of the nPowerOn bit. When enabled,  
these bits allow their corresponding function to turn  
on power to the system.  
C
Default = 0x00  
on Vbat POR  
1 = ENABLED  
0 = DISABLED  
Bit[0] SP_RI1: UART 1 Ring Indicator Pin  
Bit[1] SP_RI2: UART 2 Ring Indicator Pin  
Bit[2] SP_KDAT: Keyboard Data Pin  
Bit[3] SP_MDAT: Mouse Data Pin  
Bit[4] SP_GPINT1: Group Interrupt 1  
Bit[5] SP_GPINT2: Group Interrupt 2  
Bit[6] SP_IRRX2: IRRX2 Input Pin  
Bit[7] Reserved  
Soft Power Enable  
Register 2  
0xB1 R/W  
The following bits are the enables for the wake-up  
function of the nPowerOn bit. When enabled,  
these bits allow their corresponding function to turn  
on power to the system.  
C
Default = 0x80  
on Vbat POR  
1 = ENABLED  
0 = DISABLED  
Bit[0] SP_RXD1: UART 1 Receive Data Pin  
Bit[1] SP_RXD2: UART 2 Receive Data Pin  
Bit[2] Reserved  
Bit[3] RING Enable bit “RING_EN”  
1=Enable ring indicator on nRING pin as wakeup  
function to activate nPowerOn.  
0=Disable.  
Bit[4] VTR_POR_OFF. Controls state of nPowerOn  
after VTR POR.  
1=the nPowerOn pin will go inactive (float) and the  
machine will remain off when the VTR POR occurs.  
Software must not set VTR_POR_OFF and  
VTR_POR_EN at the same time.  
0=the nPowerOn pin will remain in the state it was in  
prior to the VTR POR (unless the VTR_POR_EN bit  
is set).  
Bit[5] Reserved  
Bit[6] VTR_POR_EN. Controls state of nPowerOn  
after VTR POR.  
1= the nPowerOn pin will go active (low) and the  
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