TABLE 47 - PC/AT AND PS/2 AVAILABLE REGISTERS
AVAILABLE REGISTERS
BASE + ADDRESS
PC-AT
PS/2 (MODEL 30)
ACCESS PERMITTED
Access to these registers DOES NOT wake up the part
00H
01H
02H
03H
04H
06H
07H
07H
----
----
DOR (1)
---
DSR (1)
---
DIR
SRA
SRB
DOR (1)
---
DSR (1)
---
R
R
R/W
---
W
---
R
W
DIR
CCR
CCR
Access to these registers wakes up the part
04H
05H
MSR
Data
MSR
Data
R
R/W
Note 1: Writing to the DOR or DSR does not wake up the part, however, writing any of the motor
enable bits or doing a software reset (via DOR or DSR reset bits) will wake up the part.
TABLE 48 - STATE OF SYSTEM PINS IN AUTO POWERDOWN
SYSTEM PINS
STATE IN AUTO POWERDOWN
INPUT PINS
nIOR
nIOW
Unchanged
Unchanged
SA[0:9]
SD[0:7]
RESET_DRV
DACKx
TC
Unchanged
Unchanged
Unchanged
Unchanged
Unchanged
OUTPUT PINS
Unchanged (low)
Unchanged
IRQx
SD[0:7]
DRQx
Unchanged (low)
FDD Interface Pins
Pins used for local logic control or part
programming are unaffected. Table 46 depicts the
state of the floppy disk drive interface pins in the
powerdown state.
All pins in the FDD interface which can be
connected directly to the floppy disk drive itself are
either DISABLED or TRISTATED.
111
SMSC [ SMSC CORPORATION ]
