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FDC37B72X_07 参数 Datasheet PDF下载

FDC37B72X_07图片预览
型号: FDC37B72X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 128引脚增强型超级I / O控制器,支持ACPI [128 Pin Enhanced Super I/O Controller with ACPI Support]
分类和应用: 控制器
文件页数/大小: 238 页 / 816 K
品牌: SMSC [ SMSC CORPORATION ]
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PARALLEL PORT FLOPPY DISK CONTROLLER  
The Floppy Disk Control signals are available  
2. Control Register read as "cable not  
connected" STROBE, AUTOFD and SLC = 0  
and nINIT =1  
3. Status Register reads: nBUSY = 0, PE = 0,  
SLCT = 0, nACK = 1, nERR = 1  
optionally on the parallel port pins. When this  
mode is selected, the parallel port is not available.  
There are two modes of operation, PPFD1 and  
PPFD2. These modes can be selected in the  
Parallel Port Mode Register, as defined in the  
Parallel Port Mode Register, Logical Device 3, at  
0xF1. PPFD1 has only drive 1 on the parallel port  
pins; PPFD2 has drive 0 and 1 on the parallel port  
pins.  
The following FDC pins are all in the high  
impedence state when the PPFDC is actually  
selected by the drive select register:  
1. nWDATA, DENSEL, nHDSEL, nWGATE,  
nDIR, nSTEP, nDS1, nDS0, nMTR0, nMTR1.  
When the PPFDC is selected the following pins  
are set as follows:  
2. If PPFDx is selected, then the parallel port  
can not be used as a parallel port until  
"Normal" mode is selected.  
1. nPDACK: high-Z  
2. PDRQ: not ECP = high-Z, ECP & dmaEn = 0,  
ECP & not dmaEn = high-Z  
3. PINTR: not active, this is hi-Z or Low  
depending on settings.  
The FDC signals are muxed onto the Parallel Port  
pins as shown in Table 42.  
Note: nPDACK, PDRQ and PINTR refer to the  
nDACK, DRQ and IRQ chosen for the parallel  
port.  
For ACPI compliance the FDD pins that are  
multiplexed onto the Parallel Port function  
independently of the state of the Parallel Port  
controller. For example, if the FDC is enabled  
onto the Parallel Port the multiplexed FDD  
interface functions normally regardless of the  
Parallel Port Power control, CR22.3. Table 41  
illustrates this functionality.  
The following parallel port pins are read as follows  
by a read of the parallel port register:  
1. Data Register (read) = last Data Register  
(write)  
TABLE 45 - PARALLEL PORT FDD CONTROL  
PARALLEL PORT FDC PARALLEL PORT  
CONTROL FDC STATE  
PARALLEL  
PARALLEL PORT  
STATE  
PORT  
POWER  
CR22.3  
LD3:CRF1.1  
LD3:CRF1.0  
1
0
X
0
0
1
X
0
0
X
1
OFF  
OFF  
ON  
ON  
OFF  
OFF  
(NOTE1)  
NOTE1: The Parallel Port Control register reads as “Cable Not Connected” when the Parallel Port FDC  
is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1.  
107  
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