(active), Vcc is > 4V, and the FDC37B72x host
interface is active. When the internal
PWRGOOD signal is “0” (inactive), Vcc is ≤ 4V,
and the FDC37B72x host interface is inactive;
that is, ISA bus reads and writes will not be
decoded.
32.768 kHz STANDBY CLOCK OUTPUT
The FDC37B72x provides a 32.768 kHz trickle
clock output pin. This output is active as long as
VTR is present.
The FDC37B72x device pins KDAT, MDAT,
IRRX, nRI1, nRI2, RXD1, RXD2, nRING,
Button_In and the GPIOs are part of the PME
interface and remain active as inputs for wakeup
when the internal PWRGOOD signal has gone
inactive, provided VTR is powered. In addition, the
nPME/SCI, GP53/IRQ11 (SCI pin), nPowerOn
and CLK32OUT pins remain active as outputs
when the internal PWRGOOD is inactive and VTR
is powered. The internal PWRGOOD signal is
also used to disable the IR Half Duplex Timeout.
OSCILLATOR
Crystal Oscillator input. A 32.768kHz crystal
connected externally on the XTAL1 and XTAL2
pins generates the 32.768kHz input clock.
Maximum clock frequency is 32.768kHz. This
oscillator is also used as an internal clock source
for functions within the FDC37B72x.
There is a bit in the Ring Filter Select Register that
can be used to select the load capacitance of the
crystal to ensure accurate time keeping. This bit is
defined as follows: Bit 6 - XTAL_CAP. This bit is
used to specify the 32kHz XTAL load
capacitance (12pF vs. 6pF):
Note: If VTR is to be used for programmable
wake-up events when VCC is removed, VTR must
be at its full minimum potential at least 10 μs
before Vcc begins a power-on cycle. When VTR
and Vcc are fully powered, the potential difference
between the two supplies must not exceed
500mV.
0=12pF (Default), 1=6pF.
114
SMSC [ SMSC CORPORATION ]
