1. ECP is not enabled in the configuration
registers.
UART POWER MANAGEMENT
2
SPP, PS/2 Parallel port or EPP mode is
selected through ecr while in ECP mode.
Direct power management is controlled by CR22.
Refer to CR22 for more information.
Exit Auto Powerdown
Auto Power Management is enabled by CR23-B4
and B5. When set, these bits allow the following
auto power management operations:
The parallel port logic can change powerdown
modes when the ECP mode is changed through
the ecr register or when the parallel port mode is
changed through the configuration registers.
1. The transmitter enters auto powerdown when
the transmit buffer and shift register are
empty.
2. The receiver enters powerdown when the
following conditions are all met:
VBAT Support
This chip requires a (TBD) MicroAmp battery
supply (VBAT) to provide battery backed up
registers. These registers retain the contents of
the general purpose registers and wake-up event
registers.
A. Receive FIFO is empty
B. The receiver is waiting for a start bit.
Note:
While in powerdown the Ring Indicator
interrupt is still valid and transitions when
the RI input changes.
VTR Support
Exit Auto Powerdown
The FDC37B72x requires
a 25 mA trickle
(standby) supply (VTR) to provide sleep current
for the programmable wake-up events in the Soft
Power Management logic, SCI, PME and SMI
The transmitter exits powerdown on a write to the
XMIT buffer. The receiver exits auto powerdown
when RXDx changes state.
interfaces when VCC is removed.
If the
FDC37B72x is not intended to provide wake-up
capabilities on standby power, VTR can be
connected to VCC. VTR powers the IR interface,
the PME registers, the PME interface, the ACPI
registers, the SCI interface, the GPIO logic, the
GPIO configuration registers and other wakeup
related configuration registers. The VTR pin
PARALLEL PORT
Direct power management is controlled by CR22.
Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B3.
When set, this bit allows the ECP or EPP logical
parallel port blocks to be placed into powerdown
when not being used.
generates
a VTR Power-on-Reset signal to
initialize certain components. All wakeup event
registers and related logic are battery backed-up
to retain the configuration of the wakeup events
upon a power loss (i.e., VCC = 0 V and VTR = 0
V). These registers are reset on a VBAT POR.
The following section lists the pins that are active
under VTR power.
The EPP logic is in powerdown under any of the
following conditions:
1. EPP is not enabled in the configuration
registers.
2. EPP is not selected through ecr while in ECP
mode.
INTERNAL PWRGOOD
An internal PWRGOOD logical control is included
to minimize the effects of pin-state uncertainty in
the host interface as Vcc cycles on and off.
When the internal PWRGOOD signal is “1”
The ECP logic is in powerdown under any of the
following conditions:
113
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