Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features
Datasheet
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Timing specifications are tested at the TTL logic levels, VIL=0.4V for a falling edge and VIH=2.4V
for a rising edge. TRI-STATE output voltage is forced to 1.4V.
Note 8.1 TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.
Note 8.2 Total Monitoring Cycle Time for cycle mode includes a one second delay plus all
temperature conversions and all analog input voltage conversions.
Note 8.3 See Table 5.2, “Conversion Cycle Timing,” on page 19 for conversion cycle timing for all
averaging options. Only the nominal default case is shown in this section.
Note 8.4 All leakage currents are measured with all pins in high impedance.
Note 8.5 The low output level for PWM pins is actually +8.0mA.
Note 8.6 The h/w monitor analog block implements a 10-bit ADC. The output of this ADC goes to
an averager block, which can be configured to accumulate the averaged value of the
analog inputs. The amount of averaging is programmable. The output of the averaging
block produces a 12-bit temperature or voltage reading value. The 8 MSbits go to the
reading register and the 4 LSbits to the A/D LSb register.
SMSC EMC6D102
Revision 0.4 (04-05-05)
DATA7S9HEET
SMSC [ SMSC CORPORATION ]
