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EMC6D100 参数 Datasheet PDF下载

EMC6D100图片预览
型号: EMC6D100
PDF下载: 下载PDF文件 查看货源
内容描述: 环境监测与治理装置带自动风扇能力的 [ENVIRONMENTAL MONITORING AND CONTROL DEVICE WITH AUTOMATIC FAN CAPABILITY]
分类和应用: 风扇装置监视器
文件页数/大小: 75 页 / 593 K
品牌: SMSC [ SMSC CORPORATION ]
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Environmental Monitoring and Control Device  
Datasheet  
enabled onto the INT# pin via the enable bits for each type of event (i.e., temperature, voltage and fan).  
See the “INTERRUPT STATUS REGISTER” section.  
The device can signal the host that it wants to talk by pulling the SMBALERT# low, if a status bit is set in  
one of the interrupt status registers and properly enabled onto the INT# pin. The host processes the  
interrupt and simultaneously accesses all SMBALERT# devices through a modified Receive Byte  
operation with the Alert Response Address (ARA).  
The EMC6D100/EMC6D101 Device, which pulled SMBALERT# low, will acknowledge the Alert Response  
Address and respond with its device address.  
The host performs a modified Receive Byte operation with the alert response address. The 7-bit device  
address provided by the EMC6D100/EMC6D101 device is placed in the 7 most significant bits of the byte.  
The eighth bit can be a zero or one.  
Table 5.5 - Modified SMBus Receive Byte Protocol Response to ARA  
ALERT  
EMC6D100/EMC6D101  
FIELD: START  
BITS:  
RESPONSE  
ADDRESS  
RD ACK  
NACK STOP  
SLAVE ADDRESS  
1
7
1
1
8
1
1
After acknowledging the slave address, the EMC6D100/EMC6D101 device will disengage the  
SMBALERT# pulldown by clearing the INT enable bit. If the condition that caused the interrupt remains,  
the Fan Control device will reassert the SMBALERT# on the next monitoring cycle, provided the INT  
enable bit has been set back to ‘1’ by software.  
EMC6D101:  
The EMC6D101 part does not have an interrupt pin. This part does not normally acknowledge or respond  
to the Alert Response Address. However, the Device will respond as described above if the INTEN bit  
(register 7Ch bit 2) is set, and if a status bit is set in one of the interrupt status registers and is properly  
enabled onto the INT# signal. Each interrupt event must be enabled into the interrupt status registers, and  
the status bits must be enabled onto the INT# signal via the enable bits for each type of event (i.e.,  
temperature, voltage and fan). See the “INTERRUPT STATUS REGISTER” section.  
SMSC EMC6D100/EMC6D101  
Page 20  
Rev. 09-09-04  
DATASHEET  
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