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EMC6D100 参数 Datasheet PDF下载

EMC6D100图片预览
型号: EMC6D100
PDF下载: 下载PDF文件 查看货源
内容描述: 环境监测与治理装置带自动风扇能力的 [ENVIRONMENTAL MONITORING AND CONTROL DEVICE WITH AUTOMATIC FAN CAPABILITY]
分类和应用: 风扇装置监视器
文件页数/大小: 75 页 / 593 K
品牌: SMSC [ SMSC CORPORATION ]
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Environmental Monitoring and Control Device  
Datasheet  
The only valid registers that are accessible by the SMBus slave address are the registers defined in the  
Registers Section. See section below for response to undefined registers.  
5.4.1 UNDEFINED REGISTERS  
Reads to undefined registers return 00h. Writes to undefined registers have no effect and return no error.  
5.5  
5.6  
General Call Address Response  
The EMC device will not respond to a general call address of 0000_000.  
Slave Device Time-Out  
According to SMBus specification, v2.0 devices in a transfer can abort the transfer in progress and release  
the bus when any single clock low interval exceeds 25ms (TTIMEOUT, MIN). Devices that have detected this  
condition must reset their communication and be able to receive a new START condition no later than  
35ms (TTIMEOUT, MAX).  
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically  
may reset its communications port after a start or stop condition  
5.7  
5.8  
5.9  
Stretching the SCLK Signal  
The EMC device supports stretching of the SCLK by other devices on the SMBus. The EMC device does  
not stretch the SCLK.  
SMBus Timing  
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing in  
the “Timing Diagram” section.  
Bus Reset Sequence  
The SMBus Slave Interface will reset and return to the idle state upon a START field followed immediately  
by a STOP field.  
5.10 SMBus Alert Response Address  
EMC6D100:  
The EMC6D100 device implements the SMBALERT# signal. The INT# interrupt pin can be used as the  
SMBALERT#. SMBALERT# is used in conjunction with the SMBus General Call Address, 0001 100. In  
order for the INT# signal to become active and for the device to respond to the Alert Response address,  
the INTEN bit (register 7Ch bit 2) must be set and the event must be properly enabled onto the INT# pin.  
Each interrupt event must be enabled into the interrupt status registers, and the status bits must be  
SMSC EMC6D100/EMC6D101  
Page 19  
Rev. 09-09-04  
DATASHEET  
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