RPM-Based Fan Controller with HW Thermal Shutdown
Datasheet
The Interrupt Status Register reports the operating condition of the EMC2103. If any of the bits are set
to a logic ‘1’ (other than HWS) then the ALERT pin will be asserted low if the corresponding channel
is enabled. Reading from the status register clears all status bits if the error conditions is removed. If
there are no set status bits, then the ALERT pin will be released.
The bits that cause the ALERT pin to be asserted can be masked based on the channel they are
associated with unless stated otherwise.
Bit 5 - TCRIT - This bit is set to ‘1’ if any bit in the Tcrit Status Register is set. This bit is automatically
cleared when the Tcrit Status Register is read and the bits are cleared.
Bit 4 - GPIO (EMC2103-2 only) - This bit is set to ‘1’ if any bit in the GPIO Status Register is set. This
bit is automatically cleared when the GPIO Status Register is read.
Bit 3 - FAN - This bit is set to ‘1’ if any bit in the Fan Status Register is set. This bit is automatically
cleared when the Fan Status Register is read and the bits are cleared.
Bit 2 - HIGH - This bit is set to ‘1’ if any bit in the High Status Register is set. This bit is automatically
cleared when the High Status Register is read and the bits are cleared.
Bit 1- LOW - This bit is set to ‘1’ if any bit in the Low Status Register is set. This bit is automatically
cleared when the Low Status Register is read and the bits are cleared.
Bit 0 - FAULT - This bit is set to ‘1’ if any bit in the Diode Fault Register is set. This bit is automatically
cleared when the Diode Fault Register is read and the bits are cleared.
6.13
Error Status Registers
Table 6.19 Error Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
EXT3
_TCR
IT
EXT2
_TCR
IT
EXT1
_TCR
IT
INT_T
CRIT
1Fh
R-C
Tcrit Status HWS
00h
EXT3
_HI
EXT2
_HI
EXT1
_HI
INT_
HI
24h
25h
26h
R-C
R-C
R-C
High Status
Low Status
Diode Fault
-
-
-
-
-
-
-
--
-
-
-
-
00h
00h
00h
EXT3
_LO
EXT2
_LO
EXT1
_LO
INT_L
O
EXT3
_FLT
EXT2
_FLT
EXT1
_FLT
-
The Error Status Registers report the specific error condition for all measurement channels with limits.
If any bit is set in the High, Low, or Diode Fault Status register, the corresponding High, Low, or Fault
bit is set in the Interrupt Status Register.
Reading the Interrupt Status Register does not clear the Error Status bit. Reading from any Error Status
Register that has bits set will clear the register and the corresponding bit in the Interrupt Status
Register if the error condition has been removed. If the error condition is persistent, reading the Error
Status Registers will have no affect.
6.13.1
Tcrit Status Register
The Tcrit Status Register stores the event that caused the SYS_SHDN pin to be asserted. Each of the
temperature channels must be associated with the SYS_SHDN pin before they can be set (see
Section 6.9). Once the SYS_SHDN# pin is asserted, it will be released when the temperature drops
below the threshold level however the individual status bit will not be cleared until read.
Revision 0.85 (01-29-08)
SMSC EMC2103
DATA5S0HEET
SMSC [ SMSC CORPORATION ]
