10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Data Register
I/O Address 04H
Memory
Data Bus
2K x 8
INTERNAL
RAM
8
D0-D7
Address Pointer Register
I/O Address 02H I/O Address 03H
High
Low
Memory
Address Bus
11-Bit Counter
11
Figure 6.2 - Sequential Access Operation
6.3
Internal RAM
The integration of the 2K x 8 RAM in the COM20022I 3V represents significant real estate savings. The
most obvious benefit is the 48 pin package in which the device is now placed (a direct result of the
integration of RAM). In addition, the PC board is now free of the cumbersome external RAM, external
latch, and multiplexed address/data bus and control functions which were necessary to interface to the
RAM. The integration of RAM represents significant cost savings because it isolates the system designer
from the changing costs of external RAM and it minimizes reliability problems, assembly time and costs,
and layout complexity.
6.3.1 Sequential Access Memory
The internal RAM is accessed via a pointer-based scheme. Rather than interfering with system memory,
the internal RAM is indirectly accessed through the Address High and Low Pointer Registers. The data is
channeled to and from the microcontroller via the 8-bit data register. For example: a packet in the internal
RAM buffer is read by the microcontroller by writing the corresponding address into the Address Pointer
High and Low Registers (offsets 02H and 03H). Note that the High Register should be written first,
followed by the Low Register, because writing to the Low Register loads the address. At this point the
device accesses that location and places the corresponding data into the data register.
The
microcontroller then reads the data register (offset 04H) to obtain the data at the specified location. If the
Auto Increment bit is set to logic "1", the device will automatically increment the address and place the
Revision 02-27-06
Page 46
SMSC COM20022I 3V
DATASHEET
SMSC [ SMSC CORPORATION ]
