10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
BIT
BIT NAME
SYMBOL
DESCRIPTION
3,2 DMA Transfer
Mode
DMAMD1, These bits select the data transfer mode of the DMA. These
DMAMD0 transfer modes influence the timing of asserting/negating the
DREQ pin.
DMAMD1 DMAMD0
Transfer Mode
Non-Burst (Default)
0
0
1
1
0
1
0
1
Burst
Programmable-Burst by Timer
Programmable-Burst by Cycle
Counter
1
0
TC Polarity
TCPOL
This bit sets the Active polarity of TC pin.
TCPOL = 0: Active High (Default), TCPOL = 1 Active Low
This bit sets the Active polarity of DREQ pin.
DREQ Polarity
DRQPOL
DRQPOL = 0: Active High (Default), DRQPOL = 1 Active
Low
Table 6.15 - DMA Count Register
SYMBOL DESCRIPTION
BIT
BIT NAME
7-0 Terminal Count
TC7-TC0
TC7-TC0: Used for non-burst or burst mode. These are the
lower 8 bits of the Terminal Count setting register. The MSB
(TC8) is in the Bus Control Register. The Terminal Count
setting range is from 1 to 512 counts (TC8 - TC0 all zeroes
means 512 counts).
TIM7-TIM0: Used for Programmable-Burst by Timer mode.
These bits are for setting the term of the continuous DMA
transfer. The time range is from 100nS to 25.6μS. The step is
100nS (TIM7-TIM0 all zeroes means 25.6μs).
CYC7-CYC0: Used for Programmable-Burst by Cycle mode.
These bits are for setting the term of the continuous DMA
transfer. The cycle range is from 2 to 256 cycles. CYC7-
CYC0 all zeroes means 256 cycles. (1 is illegal)
Timer Mode
Cycle Mode
TIM7-TIM0
CYC7-
CYC0
SMSC COM20022I 3V
Page 45
Revision 02-27-06
DATASHEET
SMSC [ SMSC CORPORATION ]
