10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
READ
DMA-MD1
REGISTER
MSB
LSB
ADDR
07-5
BUS
CONTROL
W16
X
ITCEN/
RTRG
TC8/
RSYN/
GTTM
TC4/
DMA-MD0
TCPOL
DRQ-POL
DMA
COUNT
TC7/
TIM7/
CYC7
TC6/
TIM6/
CYC6
TC5/
TIM5/
CYC5
TC3/
TIM3/
CYC3
TC2/
TIM2/
CYC2
TC1/
TIM1/
CYC1
TC0/
TIM0/
CYC0
07-6
TIM4/
CYC4
Note 6.1
This bit can be written and read.
Table 6.2 - Data Register at 16 Bit Access
BIT1
5
BIT1
4
BIT1
3
BIT1
2
BIT1
1
BIT1
0
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
BIT
BIT
1
BIT
0
REGISTER
DATA
ADDR
04
3
2
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 6.3 - Write Register Summary
WRITE
ADDR
00
MSB
LSB
REGISTER
INTERRUPT
MASK
NEW
RECON
RI/TR1
0
0
DMA
END
C4
EXCNAK
TA/
TTA
C0
NEXTID
COMMAND
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA*
01
02
C7
C6
AUTO-
INC
C5
0
C3
C2
C1
A9
RD-DATA
0
DMAEN
A10
A8
03
A7
A6
A5
A4
A3
D3
A2
A1
A0/ SWAP
04
05
D7
D6
0
D5
0
D4
0
D2
D1
D0
SUB-
AD0
(R/W)*
(R/W)
(Note 6.2)
SUB-AD2
SUB- AD1
SUBADR
06
RESET
CCHEN
TXEN
ET1
ET2
BACK-
PLANE
TID2
SUB-
AD1
SUB-
AD0
CONFIG-
URATION
TENTID
07-0
07-1
07-2
TID7
NID7
TID6
NID6
FOUR
NAKS
0
TID5
NID5
0
TID4
NID4
RCV-
ALL
TID3
NID3
CKP3
TID1
NID1
CKP1
TID0
NID2
NID0
SLOW-ARB
NODEID
SETUP1
P1-MODE
CKP2
07-3
07-4
0
0
0
0
0
0
0
TEST
RBUS-
TMG
0
CKUP1
CKUP0
EF
NO-
RCN-
TM1
RCN-
TM0
SETUP2
SYNC
DMA-
MD0
07-5
07-6
W16
0
ITCEN/
RTRG
TC8/
RSYN/
GTTM
TC4/
DMA-
MD1
TC-POL
DRQ-POL
BUS
CONTROL
TC7/
TIM7/
CYC7
TC6/
TIM6/
CYC6
TC5/
TIM5/
CYC5
TC3/
TIM3/
CYC3
TC2/
TIM2/
CYC2
TC1/
TIM1/
CYC1
TC0/
TIM0/
CYC0
DMA
COUNT
TIM4/
CYC4
SMSC COM20022I 3V
Page 31
Revision 02-27-06
DATASHEET
SMSC [ SMSC CORPORATION ]
