10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Note 6.2 This bit can be written and read.
Table 6.4 - Data Register at 16 Bit Address
BIT1
5
BIT1
4
BIT1
3
BIT1
2
BIT1
1
BIT1
0
BIT9
BIT8
BIT7
BIT6
BIT5
BIT4
D4
BIT3
D3
BIT2
D2
BIT1
D1
BIT0
D0
REGISTER
DATA
ADDR
04
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
6.2
Internal Registers
The COM20022I 3V contains 16 internal registers. Table 6.1 and Table 6.3 illustrate the COM20022I 3V
register map. All undefined bits are read as undefined and must be written as logic "0".
6.2.1 Interrupt Mask Register (IMR)
The COM20022I 3V is capable of generating an interrupt signal when certain status bits become true. A
write to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the
IMR are in the same position as their corresponding status bits in the Status Register and Diagnostic
Status Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits
capable of generating an interrupt include the Receiver Inhibited bit, DMAEND bit (new to the COM20022I
3V), New Next ID bit, Excessive NAK bit, Reconfiguration Timer bit, and Transmitter Available bit.
DMAEND bit is inverted DMAEN bit on ADDRESS PTR High register. No other Status or Diagnostic
Status bits can generate an interrupt.
The six maskable status bits are ANDed with their respective mask bits, and the results are ORed to
produce the interrupt signal. An RI or TA interrupt is masked when the corresponding mask bit is reset to
logic "0", but will reappear when the corresponding mask bit is set to logic "1" again, unless the interrupt
status condition has been cleared by this time. A RECON interrupt is cleared when the "Clear Flags"
command is issued. An EXCNAK interrupt is cleared when the "POR Clear Flags" command is issued. A
New Next ID interrupt is cleared by reading the Next ID Register. If the DMAEND bit is not masked, the
interrupt occurs by finishing the DMA operation. The Interrupt Mask Register defaults to the value 0000
0000 upon hardware reset.
6.2.2 Data Register
This read/write 8-bit register is used as the channel through which the data to and from the RAM passes.
The data is placed in or retrieved from the address location presently specified by the address pointer.
The contents of the Data Register are undefined upon hardware reset. In case of READ operation, the
Data Register is loaded with the contents of COM20022I 3V Internal Memory upon writing Address Pointer
low only once.
The SWAP bit is used to swap the upper and lower data byte. The SWAP bit is located at bit 0 of
ADDRESS PTR_LOW register. When 16 bit access is enabled, (W16=1), A0 becomes the SWAP bit.
6.2.3 Tentative ID Register
The Tentative ID Register is a read/write 8-bit register accessed when the Sub Address Bits are set up
accordingly (please refer to the Configuration Register and SUB ADR Register). The Tentative ID Register
can be used while the node is on-line to build a network map of those nodes existing on the network. It
minimizes the need for operator interaction with the network. The node determines the existence of other
nodes by placing a Node ID value in the Tentative ID Register and waiting to see if the Tentative ID bit of
the Diagnostic Status Register gets set. The network map developed by this method is only valid for a
short period of time, since nodes may join or depart from the network at any time. When using the
Revision 02-27-06
Page 32
SMSC COM20022I 3V
DATASHEET
SMSC [ SMSC CORPORATION ]
