10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Board RAM
Datasheet
Chapter 6 Functional Description
6.1
Microsequencer
The COM20022I 3V contains an internal microsequencer which performs all of the control operations
necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program
counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and
reconfiguration logic.
The COM20022I 3V derives a 20 MHz and a 10 MHz clock from the output clock of the Clock Multiplier.
These clocks provide the rate at which the instructions are executed within the COM20022I 3V. The 20
MHz clock is the rate at which the program counter operates, while the 10 MHz clock is the rate at which
the instructions are executed. The microprogram is stored in the ROM and the instructions are fetched
and then placed into the instruction registers. One register holds the opcode, while the other holds the
immediate data. Once the instruction is fetched, it is decoded by the internal instruction decoder, at which
point the COM20022I 3V proceeds to execute the instruction. When a no-op instruction is encountered,
the microsequencer enters a timed loop and the program counter is temporarily stopped until the loop is
complete. When a jump instruction is encountered, the program counter is loaded with the jump address
from the ROM. The COM20022I 3V contains an internal reconfiguration timer which interrupts the
microsequencer if it has timed out. At this point the program counter is cleared and the MYRECON bit of
the Diagnostic Status Register is set.
Table 6.1 - Read Register Summary
READ
REGISTER
MSB
LSB
TA/
TTA
X
ADDR
00
STATUS
RI/TRI
X/RI
DUPID
AUTO-INC
A6
X/TA
RCV-ACT
X
POR
TOKEN
X
TEST
EXC-NAK
DMA-EN
A3
RECON
TENTID
A10
TMA
NEW
DIAG.
MY-
RECON
01
02
03
NEXTID
STATUS
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
DATA*
RD-DATA
A7
A9
A8
A5
A4
A2
A1
A0/ SWAP
D7
D6
0
D5
0
D4
0
D3
D2
D1
D0
04
05
SUB ADR
(R/W)*
(R/W)
SUB-AD2
SUB-AD1
SUB-AD0
(Note 6.1)
CONFIG-
URATION
TENTID
RESET
CCHEN
TXEN
ET1
ET2
BACK-
PLANE
SUB-AD1
SUB-AD0
06
TID7
NID7
TID6
NID6
TID5
NID5
X
TID4
NID4
TID3
NID3
CKP3
TID2
NID2
CKP2
TID1
NID1
CKP1
TID0
NID0
07-0
07-1
07-2
NODE ID
SETUP1
P1 MODE
FOUR
NAKS
NXT ID6
RCV- ALL
SLOW-
ARB
NEXT ID
SETUP2
NXT ID7
NXT ID5
CKUP1
NXT ID4
CKUP0
NXT ID3
EF
NXT
ID2
NXT ID1
NXT ID0
07-3
07-4
RBUS-
TMG
X
NO-SYNC
RCN-TM1
RCM-TM2
Revision 02-27-06
Page 30
SMSC COM20022I 3V
DATASHEET
SMSC [ SMSC CORPORATION ]
