5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Datasheet
nTXEN
t1
t13
t3
t2
nPULSE1
t9
t8
LAST BIT
(400 nS BIT TIME)
t4
t5
t6
nPULSE2
(Internal Clk)
t7
t10
t12
RXIN
t11
Parameter
min typ max units
-25
50
nPULSE2 High to nTXEN Low
t1
t2
t3
t4
t5
t6
t7
t8
nS
nPULSE1 Pulse Width
nPULSE1 Period
nPULSE2 Low to nPULSE1 Low
nPULSE2 High Time
nPULSE2 Low Time
nPULSE2 Period
200*
400*
nS
nS
nS
nS
nS
nS
nS
-25
50
100*
100*
200*
50
nPULSE2 High to nTXEN High
-25
(First Rising Edge on nPULSE2 after Last Bit Time)
nTXEN Low to first nPULSE1 Low**
Beginning Last Bit Time to nTXEN High**
650
450
750
550
t9
t13
nS
nS
t10
t11
t12
10
RXIN Active Pulse Width
RXIN Period
RXIN Inactive Pulse Width
200*
400*
nS
nS
nS
20
Above values are for 2.5 Mbps.
Other Data Rates are shown below.
TDR is the Data Rate Period
*t5, t6 = TDR/4
*t2, t7, t10 = TDR/2
*t3, t11 = TDR
7
4
**t9 = x TDR +/- 50 nS
5
**t13 = x TDR +/- 50 nS
4
Figure 8.12 - Backplane Mode Transmit or Receive Timing
(These signals are to and from the differential driver or the cable)
Revision 12-05-06
Page 64
SMSC COM20020I Rev D
DATASHEET
SMSC [ SMSC CORPORATION ]
