Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 20.33 SGPIO Direction Register J
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7FAD
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
R/W
D2
R/W
D1
R/W
D0
R/W
R
R
R
R
HOST TYPE
Reserved
Reserved Reserved Reserved SGPIO33 SGPIO32 SGPIO31 SGPIO30
1=output 1=output 1=output 1=output
BIT NAME
0=input
0=input
0=input
0=input
20.6
GPIO Pass-Through Ports
The LPC47N350 includes four GPIO Pass-Through Ports. GPIO Pass-Through Ports require two
general purpose I/O pins and a multiplexer (See Figure 20.4). The GPIO Pass-Through Port (GPTP)
can connect either the GPIOm pin or GPIOn to the GPIOn pin. The GPTPs are controlled by the PTMUX
bits found in the GPIO Pass-Through Port Mux Register (See Section 20.6.1, "GPIO Pass-Through Port
Mux Register"). The four GPTPs and their related PTMUX bits are shown in Figure 20.4.
PTMUXn
1
GPIOn PIN
MUX
0
GPIOm PIN
GPIOm
GPIOn
Figure 20.4 GPIO Pass-Through Port
Note: Figure 20.4 is for illustration purposes only and is not intended to suggest specific
implementation details.
Table 20.34 Four GPIO Pass-Through Ports
GPIO PAIR (SEE Note 20.11)
GPIOM (SEE
Note 20.13)
GPION
LGPIO60
MUX CONTROL (SEE Note 20.12)
LGPIO50
PTMUX1
237
SMSC LPC47N350
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
