Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Registers 0x60 and 0x61 are the LPC LGPIO Primary Base Address register. Register 0x60 is the LPC
LGPIO Primary Base Address High Byte, register 0x61 is the LPC LGPIO Primary Base Address Low
Byte.
Note 20.8 The LPC LGPIO Base is relocatable on 16-byte boundaries; i.e., bits D0-D3 in the LPC
LGPIO Primary Base Address Low Byte must be “0”. Valid LPC LGPIO runtime register base
address values are between 0x0000-0x0FF0.
Table 20.14 LPC LGPIO Block Configuration Registers (LDN A)
VCC1
&
DESCRIPTION
HARD
SOFT
VCC2
POR
VCC0
POR
INDEX
TYPE
RESET
RESET
D7 D6 D5 D4
D3
D2
D1
D0
0x30
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
-
-
-
Activate
RESERVED
Activate
060
R/W
R/W
LPC LGPIO Block Primary Base Address High Byte
“0” “0” “0” “0” A11 A10 A9 A8
LPC LGPIO BLock Primary Base Address Low Byte
A7 A6 A5 A4 A3 “0” “0” “0”
0x61
20.4.2 LGPIO LPC Runtime Registers
The base address and activation control for these registers are located in the LPC Configuration
Registers in Logical Device Ah.
Table 20.15 LPC LGPIO Runtime Registers
BASE
LPC SELECT
ADDRESS
OFFSET
REGISTER
TYPE
REGISTER BIT
REGISTER NAME
D0
0
1
2
3
4
5
R/W
R
LGPIO DIRECTION REGISTER G
LGPIO INPUT REGISTER G
LGPIO OUTPUT REGISTER G
LGPIO DIRECTION REGISTER H
LGPIO INPUT REGISTER H
LGPIO OUTPUT REGISTER H
R/W
D1
R
R/W
Note 20.9 The LPC SELECT bits determine the register source for the LGPIO pins (see Section
20.4.3.3, "LPC Select Register"). Register access is unaffected by the state of the LPC
SELECT bits. For example, if the LPC GPIO runtime registers are active, the LGPIO
Direction Register G can read and write even if the LPC SELECT register bit D0 is
deasserted.
SMSC LPC47N350
227
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
