Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 20.12 Out Register E
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F23
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 TYPE
BIT NAME
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
R/W
OUT11
OUT10
OUT9
OUT8
20.4
LPC/8051-Addressable GPIOs
The LPC47N350 includes eight LPC/8051-addressable LGPIO pins LGPIO50-LGPIO53, LGPIO60-
LGPIO63 (See Table 2.1 and Table 2.2).
The output pin buffer type for LGPIO60-63 can be programmed by the 8051 as open-drain or push-pull
(Section 20.4.3.4).
LGPIO50-LGPIO53 can generate 8051 interrupts and wake events. See Section 7.9, "8051 Interrupts".
An interrupt will occur on either edge of signals connected to any LGPIO50-LGPIO53 pin configured as
an input.
The LGPIO pins can be accessed either by the LPC host or the 8051 depending on the state of a group
LPC SELECT bit (See Section 20.4.3.3). There are two 4-pin LGPIO groups. Host selection is
determined by the 8051 per 4-pin group.
There are separate 8051 and LPC runtime register sets to control the LGPIO pins (See Section 20.4.2
and Section 20.4.3).
The 8051 is responsible for configuring the LGPIO interface including the LPC SELECT bits and the
output pin buffer type.
When the LPC host is selected to control an LGPIO pin and PWRGD is deasserted, the pin is tristated
(input). Otherwise, the LGPIO channel direction and logic state is determined by the runtime registers
of the selected host (See Table 20.13, "LPC Addressable GPIO Direction Control" and Figure 20.2, "LPC
Addressable GPIO Block Diagram").
SMSC LPC47N350
225
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
