Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 20.13 LPC Addressable GPIO Direction Control
8051
DIR
LPC
LPC DIR
SEL.
PWRGD
PIN DIR
IN
COMMENTS
1.
X
X
1
0
0
GPIO pin tristates (input) because GPIO
is LPC type & VCC2 is invalid.
2.
3.
4.
5.
1
0
X
1
OUT
IN
GPIO pin is LPC type, follows LPC DIR
bit & VCC2 is valid.
1
0
X
OUT
IN
GPIO pin is 8051 type, follows 8051 DIR
bit & VCC2 is not required.
PWRGD
LPC DIR`
LPC SELECT
8051 DIR
LPC SELECT
LPC OUT
1
0
LGPIOn
8051 OUT
LPC IN
8051 IN
Figure 20.2 LPC Addressable GPIO Block Diagram
Note 20.7 This figure is for illustration purposes only and is not intended to suggest specific
implementation details.
20.4.1 LPC LGPIO Base Address
Logical Device Number Ah in the LPC47N350 provides the base address and activation control for the
8 LPC/8051-addressable GPIO pins.
Register 0x30 is the Activate register. The activation control (LDNA:CR30.0) qualifies address decoding
for the LPC LGPIO runtime registers; e.g., if the Activate bit D0 in the Activate register is “0”, the LPC
LGPIO runtime register addresses will not be decoded; if the Activate bit is “1”, these addresses will be
decoded depending on the values programmed in the LPC LGPIO Primary Base Address registers.
Revision 1.1 (01-14-03)
226
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
