ST8024T
7.
7.1
FUNCTIONAL DESCRIPTION
Pin Functions
FUNCTION
Logic system power supply pin,
Connected to +2.5 to +5.5 V.
Ground pin
Logic ground pin
Do not short LGND with GND and Vss by ITO on LCD panel
Connect it to GND on PCB or FPC.
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider
Ensure that voltages are set such that V
SS
< V
43
< V
12
< V
0
.
V
iL
and V
iR
(i = 0,12, 43) must connect to an external power supply, and supply regular
voltage which is assigned by specification for each power pin
Input pins for display data
In 4-bit parallel mode, DI
3
-DI
0
are the display data input pins, and DI
7
-DI
4
must be
connected to LGND or V
DD
.
In 8-bit parallel mode, All DI
7
-Dl
0
pins are the display data input pins.
Refer to section 7.2.2.
Clock input pin for taking display data
Data is read at the falling edge of the clock pulse.
Latch pulse input pin for display data
Data is latched at the falling edge of the clock pulse.
Input pin for selecting the reading direction of display data
When set to LGND level "L", data is read sequentially from Y
240
to Y
1
.
When set to V
DD
level "H", data is read sequentially from Y
1
to Y
240
.
Refer to section 7.2.2.
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
When set to LGND level "L", the LCD drive output pins (Y
1
-Y
240
) are set to level Vss.
When set to "L", the contents of the line latch are reset, but the display data are read in
the
data latch regardless of the condition of /DISPOFF. When the /DISPOFF function is
canceled, the driver outputs non-select level (V
12
or V
43
), then outputs the contents of
the data latch at the next falling edge of the LP. At that time, if /DISPOFF removal time
does not correspond to what is shown in AC characteristics, it can not output the
reading data correctly.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the line latch output
signal and the FR signal.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
When set to LGND level "L", 8-bit parallel input mode is set.
When set to V
DD
level "H", 4-bit parallel input mode is set.
Refer to section 7.2.2.
Segment mode/common mode selection pin
When set to V
DD
level "H", segment mode is set.
Input/output pins for chip selection
When L/R input is at LGND level "L", ElO
1
is set for output, and EIO
2
is set for input.
When L/R input is at V
DD
level "H", ElO
1
is set for input, and EIO
2
is set for output.
(Segment mode)
SYMBOL
V
DD
GND
LGND
V
SS
V
0L
, V
0R
V
12L
, V
12R
V
43L
, V
43R
DI
7
-DI
0
XCK
LP
L/R
/DISPOFF
FR
MD
S/C
ElO
1
, EIO
2
Preliminary Ver 0.12
Page 7/26
2008/01/24
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
