ST8024T
7.2.2
Relationship between the display data and LCD drive output Pins
(Segment Mode)
(a) 4-bit Parallel Input Mode
DATA
INPUT
DI0
Dl1
DI2
DI3
DI0
Dl1
DI2
NUMBER OF CLOCKS
60 CLOCK 59 CLOCK 58 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK
MD L/R EIO1
EI02
Y1
Y2
Y5
Y6
Y9
Y10
…
…
…
…
…
…
…
…
Y229
Y230
Y231
Y232
Y12
Y233
Y234
Y235
Y236
Y8
Y237
Y238
Y239
Y240
Y4
H
H
L Output Input
Y3
Y7
Y11
Y4
Y8
Y12
Y240
Y239
Y238
Y237
Y236
Y235
Y234
Y233
Y232
Y231
Y230
Y229
Y11
Y10
Y9
Y7
Y6
Y5
Y3
Y2
Y1
H
Input Output
DI3
(b) 8-bit Parallel Input Mode
DATA
INPUT
DI0
Dl1
DI2
DI3
DI4
DI5
DI6
DI7
DI0
Dl1
DI2
DI3
DI4
Dl5
DI6
DI7
NUMBER OF CLOCKS
30 CLOCK 29 CLOCK 28 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK
MD L/R EIO1
EI02
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y240
Y239
Y238
Y237
Y236
Y235
Y234
Y233
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y232
Y231
Y230
Y229
Y228
Y227
Y226
Y225
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y224
Y223
Y222
Y221
Y220
Y219
Y218
Y217
…
…
…
…
Y217
Y218
Y219
Y220
Y221
Y222
Y223
Y224
Y24
Y225
Y226
Y227
Y228
Y229
Y230
Y231
Y232
Y16
Y233
Y234
Y235
Y236
Y237
Y238
Y239
Y240
Y8
L
L
L Output Input
…
…
…
…
…
…
…
…
Y23
Y15
Y7
Y22
Y14
Y6
Y21
Y13
Y5
H
Input Output
Y20
Y12
Y4
Y19
Y11
Y3
Y18
Y10
Y2
Y17
Y9
Y1
(Common Mode)
MD
L
(Single)
L/R
L
H
DATA TRANSFER DIRECTION
Y240 → Y1
EIO1
Output
Input
EI02
Input
Output
DI7
X
X
Y1 → Y240
Y240 → Y121
Y120 → Y1
Y1 → Y120
Y121 → Y240
L
Output
Input
Input
Input
Input
H
(Dual)
H
Output
NOTES:
ꢂ L: LGND (0 V), H: VDD (+2.5 to +5.5 V), X: Don't care
ꢂ "Don't care" should be fixed to "H" or "L", avoiding floating.
Preliminary Ver 0.12
Page 10/26
2008/01/24
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
