ST8024T
3.
BLOCK DIAGRAM
V
0R
V
12R
V
43R
V
SS
Y
1
Y
2
Y
239
Y
240
FR
/DISPOFF
LEVEL
SHIFTER
V
SS
240-BIT 4-LEVEL DRIVER
240
V
43L
V
12L
V
0L
EIO
1
EIO
2
ACTIVE
CONTROL
240-BIT LEVEL SHIFTER
240
240-BIT LINE LATCH/SHIFT REGISTER
16
8 BIT
DATA
LATCH
16
16
LP
XCK
CONTROL
LOGIC
8
L/R
MD
S/C
SP CONVERSION & DATA CONTROL
(4 to 8 or 8 to 8)
DATA CONTROL
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
V
DD
V
SS
4.
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
FUNCTION
In case of segment mode, controls the selection or non-selection of the chip. Following
an LP signal input, and after the chip selection signal is input, a selection signal is
generated internally until 240 bits of data have been read in. Once data input has been
Active Control
completed, a selection signal for cascade connection is output, and the chip is
non-selected. In case of common mode, controls the input/output data of bi-directional
pins.
In case of segment mode, keeps input data which are 2 clocks of XCK at 4-bit parallel
SP Conversion
input mode in latch circuit, or keeps input data which are 1 clock of XCK at 8-bit parallel
& Data Control
input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time.
In case of segment mode, selects the state of the data latch which reads in the data bus
Data Latch Control signals. The shift direction is controlled by the control logic. For every 16 bits of data
read in, the selection signal shifts one bit based on the state of the control circuit.
In case of segment mode, latches the data on the data bus. The latch state of each LCD
Data Latch
drive output pin is controlled by the control logic and the data latch control; 240 bits of
data are read in 30 sets of 8 bits.
In case of segment mode, all 240 bits which have been read into the data latch are
Line Latch/
simultaneously latched at the falling edge of the LP signal, and are output to the level
Shift Register
shifter block. In case of common mode, shifts data from the data input pin at the falling
edge of the LP signal.
Level Shifter
The logic voltage signal is level-shifted to the LCD drive voltage level, and is output to
the driver block.
Drives the LCD drive output pins from the line latch/shift register data, and selects one of
4-Level Driver
4 levels (V
0
, V
12
, V
43
or Vss) based on the S/C, FR and /DISPOFF signals.
Controls the operation of each block. In case of segment mode, when an LP signal has
been input, all blocks are reset and the control logic waits for the selection signal output
Control Logic
from the active control block. Once the selection signal has been output, operation of the
data latch and data transmission is controlled, 240 bits of data are read in, and the chip
is non-selected. In case of common mode, controls the direction of data shift.
Preliminary Ver 0.12
Page 3/26
2008/01/24
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
