ST8024T
ꢂDuring output, set to "H" while LP • XCK is "H" and after 240 bits of data have been
read, set
to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to
"H".
ꢂDuring input, the chip is selected while El is set to "L" after the LP signal is input. The
chip is non-selected after 240 bits of data have been read.
LCD drive output pins
ꢂCorresponding directly to each bit of the data latch, one level (V0, V12, V43, or VSS) is
selected and output.
Y1 -Y240
ꢂTable of truth values is shown in "TRUTH TABLE" in Functional Operations.
(Common mode)
SYMBOL
VDD
FUNCTION
Logic system power supply pin, connected to +2.5 to +5.5 V.
Ground pin
GND
Logic ground pin
LGND
ꢂ Do not short LGND with GND and Vss by ITO on LCD panel
ꢂ Connect it to GND on PCB or FPC.
VSS
Connect to GND by ITO on LCD panel.
Bias power supply pins for LCD drive voltage
V0L, V0R
V12L, V12R
V43L, V43R
ꢂNormally use the bias voltages set by a resistor divider.
ꢂEnsure that voltages are set such that VSS < V43 < V12 < V0.
ꢂViL and ViR (i = 0,12, 43) must connect to an external power supply, and supply regular
voltage which is assigned by specification for each power pin.
Shift data input/output pin for bi-directional shift register
ꢂOutput pin when L/R is at LGND level "L', input pin when L/R is at VDD level "H".
ꢂWhen L/R = H, ElO1 is used as input pin, it will be pulled down.
ꢂWhen L/R = L, ElO1 is used as output pin, it won't be pulled down.
ꢂRefer to section 7.2.2.
Shift data input/output pin for bi-directional shift register
ꢂInput pin when L/R is at LGND level "L", output pin when L/R is at VDD level "H".
ꢂWhen L/R = L, EIO2 is used as input pin, it will be pulled down.
ꢂWhen L/R = H, EIO2 is used as output pin, it won't be pulled down.
ꢂRefer to section 7.2.2.
ElO1
EIO2
Shift clock pulse input pin for bi-directional shift register
ꢂData is shifted at the falling edge of the clock pulse.
Input pin for selecting the shift direction of bi-directional shift register
ꢂData is shifted from Y240 to Y1 when set to LGND level "L", and data is shifted from Y1 to
Y240 when set to VDD level "H".
LP
L/R
ꢂRefer to section 7.2.2.
Control input pin for output of non-select level
ꢂThe input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
ꢂWhen set to LGND level "L", the LCD drive output pins (Y1-Y240) are set to level LGND.
ꢂWhen set to "L”, the contents of the shift register are reset to not reading data. When
the /DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), and
the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF
removal time does not correspond to what is shown in AC characteristics, the shift data
is not read correctly.
/DISPOFF
ꢂTable of truth values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
ꢂThe input signal is level-shifted from logic voltage level to LCD drive voltage level, and
controls the LCD drive circuit.
FR
ꢂNormally it inputs a frame inversion signal.
ꢂThe LCD drive output pins' output voltage levels can be set using the shift register
output signal and the FR signal.
ꢂTable of truth values is shown in "TRUTH TABLE" in Functional Operations.
Mode selection pin
MD
ꢂWhen set to LGND level "L", single mode operation is selected; when set to VDD level
Preliminary Ver 0.12
Page 8/26
2008/01/24
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
