ST7578
Power OFF Flow and Sequence
By setting PD=”1”, ST7578 will go into power save mode. The LCD driving outputs are fixed to VSS, built-in power circuits
are turned OFF and a discharge process starts.
Instruction Flow
After the built-in power circuits are turned OFF and
completely discharged, the power (VDD1 and VDD2)
can be removed.
Note:
1. tIPOFF: Internal Power discharge time. => 250ms (max).
2. tV2OFF: Period between VDD1 and VDD2 OFF time. => 0 ms (min).
3. It is NOT recommended to turn VDD1 OFF before VDD2. Without VDD1, the internal status cannot be guaranteed and
internal discharge-process maybe stopped. The un-discharged power maybe flows into COM/SEG output(s) and the
liquid crystal in panel maybe polarized.
4. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON.
5. The timing is dependent on panel loading and the external capacitor(s).
6. The timing in these figures is base on the condition that: LCD Panel Size = 1.4” with C1=1uF, C2=1uF.
7. When turning VDD2 OFF, the falling time should follow the specification:
300ms ≤ tPFall ≤ 1sec
8. If the power OFF flow cannot meet this specification, it is recommended to use the resistor shown in application circuits
(about 500KΩ ~ 1MΩ).
Ver 1.2
33/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
