ST7578
10. COMMAND SEQUENCE
This section introduces some reference operation flows.
Power ON flow and instruction sequence:
Operating Flow
Power ON
Keep RESB=L
Wait power stable, t>1ms
(depends on system power)
Set RESB=H
Wait reset finished, t>5us
Initial: Power Circuit
[ Function Set ] PD=L, H=1
[ Bias System ]
[ Set V0 ]
[ Function Set ] PD=L, H=0
[ Set V0 Range ]
Delay 50ms
Initial: LCM Circuit
[ Other Settings ]
(Address, MX, MY and etc.)
Write DDRAM
[ Display ON ]
Normal Operating
Power Sequence
1. tV2ON: VDD2 power ON delay.
=> 0 ≤ tV2ON ≤ No Limitation.
2. tRSTL: Reset Low time after VDD1 is stable.
=> 0 ≤ tRSTL ≤ 50 ms*1.
3. tRW: Reset low pulse width.
Please refer to RESB timing specification.
Note:
1. IC will NOT be damaged if either VDD1 or VDD2 is OFF while another is ON. The specification listed here is to prevent
abnormal display on LCD module.
2. Be sure the power is stable and the internal reset is finished (refer to RESB timing specification).
Ver 1.2
32/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
