ST7578
9. INSTRUCTION DESCRIPTION
H=0 or 1 (H-Flag Independent)
Function Set
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
MX
MY
PD
V
H
Flag
Description
SEG bi-direction selection
MX
MX=0: normal direction (SEG0->SEG101)
MX=1: reverse direction (SEG101->SEG0)
COM bi-direction selection
MY
PD
MY=0: normal direction (COM0->COM66)
MY=1: reverse direction (COM66->COM0)
PD=0: chip is active
PD=1: chip is in power down mode
All LCD outputs at VSS (display off), bias generator and V0 generator off, VOUT can be disconnected,
oscillator off (external clock possible), RAM contents not cleared; RAM data can be written.
Select addressing mode: V=0 for Horizontal Addressing; V=1 for Vertical Addressing.
H=0: Basic Instruction set;
V
H
H=1: Extended instruction set.
Data access can be used in both instruction blocks. Refer to the instruction table.
Read Status
Indicates the internal status of ST7578.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
PD
0
0
D
E
MX
MY
DO
Flag
Description
PD=0: chip is active
PD=1: chip is in power down mode
PD
D
0
0
1
1
E
0
1
0
1
The bits D and E select the display mode.
Display OFF
D,E
DO
All display segments on
Normal mode
Inverse video mode
DO=0: D7 (MSB) is on top
DO=1: D0 (LSB) is on top
Refer to page 23.
Read Data
By specify the column address and page address, the display data in DDRAM can be read by MPU (parallel interface).
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
1
1
Read Data
Write Data
8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and
page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data
to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written.
A0
R/W(RWR)
D7
D6
D5
D4
D3
D2
D1
D0
1
0
Write Data
Ver 1.2
28/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
