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U632H64BS2K25G1 参数 Datasheet PDF下载

U632H64BS2K25G1图片预览
型号: U632H64BS2K25G1
PDF下载: 下载PDF文件 查看货源
内容描述: PowerStore 8K ×8的nvSRAM [PowerStore 8K x 8 nvSRAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 15 页 / 410 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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U632H64  
Device Operation  
Figure 1 shows the proper connection of capacitors for  
automatic STORE operation. The charge storage capa-  
citor should have a capacity of 100 μF ( 20 %) at 6 V.  
Each U632H64 must have its own 100 μF capacitor.  
Each U632H64 must have a high quality, high fre-  
quency bypass capacitor of 0.1 μF connected between  
The U632H64 has two separate modes of operation:  
SRAM mode and nonvolatile mode. In SRAM mode,  
the memory operates as a standard fast static RAM. In  
nonvolatile mode, data is transferred from SRAM to  
EEPROM (the STORE operation) or from EEPROM to  
SRAM (the RECALL operation). In this mode SRAM  
functions are disabled.  
STORE cycles may be initiated under user control via a  
software sequence or HSB assertion and are also auto-  
matically initiated when the power supply voltage level  
of the chip falls below VSWITCH. RECALL operations are  
automatically initiated upon power up and may occur  
also when VCCX rises above VSWITCH after a low power  
condition. RECALL cycles may also be initiated by a  
software sequence.  
VCAP and VSS, using leads and traces that are as short  
as possible. This capactior do not replace the normal  
expected high frequency bypass capacitor between the  
power supply voltage and VSS.  
In order to prevent unneeded STORE operations, auto-  
matic STOREs as well as those initiated by externally  
driving HSB LOW will be ignored unless at least one  
WRITE operation has taken place since the most  
recent STORE cycle. Note that if HSB is driven LOW  
via external circuitry and no WRITEs have taken place,  
the part will still be disabled until HSB is allowed to  
return HIGH. Software initiated STORE cycles are per-  
formed regardless of whether or not a WRITE opera-  
tion has taken place.  
SRAM READ  
The U632H64 performs a READ cycle whenever E and  
G are LOW and HSB and W are HIGH. The address  
specified on pins A0 - A12 determines which of the  
8192 data bytes will be accessed. When the READ is  
initiated by an address transition, the outputs will be  
valid after a delay of tcR. If the READ is initiated by E or  
G, the outputs will be valid at ta(E) or at ta(G), whichever  
is later. The data outputs will repeatedly respond to  
address changes within the tcR access time without the  
need for transition on any control input pins, and will  
remain valid until another address change or until E or  
G is brought HIGH or W or HSB is brought LOW.  
Automatic RECALL  
During power up an automatic RECALL takes place. At  
a low power condition (power supply voltage < VSWITCH  
)
an internal RECALL request may be latched. As soon  
as power supply voltage exceeds again the sense  
voltage of VSWITCH, a requested RECALL cycle will  
automatically be initiated and will take tRESTORE to com-  
plete.  
If the U632H64 is in a WRITE state at the end of a  
power up RECALL, the SRAM data will be corrupted.  
To help avoid this situation, a 10 KΩ resistor should be  
connected between W and power supply voltage.  
SRAM WRITE  
A WRITE cycle is performed whenever E and W are  
LOW and HSB is HIGH. The address inputs must be  
stable prior to entering the WRITE cycle and must  
remain stable until either E or W goes HIGH at the end  
of the cycle. The data on pins DQ0 - 7 will be written  
into the memory if it is valid tsu(D) before the end of a W  
controlled WRITE or tsu(D) before the end of an E con-  
trolled WRITE.  
It is recommended that G is kept HIGH during the  
entire WRITE cycle to avoid data bus contention on the  
common I/O lines. If G is left LOW, internal circuitry will  
turn off the output buffers tdis(W) after W goes LOW.  
Software Nonvolatile STORE  
The U632H64 software controlled STORE cycle is  
initiated by executing sequential READ cycles from six  
specific address locations. By relying on READ cycles  
only, the U632H64 implements nonvolatile operation  
while remaining compatible with standard 8K x 8  
SRAMs. During the STORE cycle, an erase of the pre-  
vious nonvolatile data is performed first, followed by  
parallel programming of all nonvolatile elements. Once  
a STORE cycle is initiated, further inputs and outputs  
are disabled until the cycle is completed.  
Because a sequence of addresses is used for STORE  
initiation, it is important that no other READ or WRITE  
accesses intervene in the sequence or the sequence  
will be aborted.  
To initiate the STORE cycle the following READ  
sequence must be performed:  
Automatic STORE  
During normal operation, the U632H64 will draw cur-  
rent from VCCX to charge up a capacitor connected to  
the VCAP pin. This stored charge will be used by the  
chip to perform a single STORE operation. If the  
voltage on the VCCX pin drops below VSWITCH, the part  
will automatically disconnect the VCAP pin from VCCX  
and initiate a STORE operation.  
August 15, 2006  
STK Control #ML0047  
11  
Rev 1.1