STK22C48
HARDWARE MODE SELECTION
E
W
HSB
A
- A (hex)
MODE
I/O
Output High Z
Output Data
Input Data
POWER
Standby
NOTES
12
0
H
L
X
H
L
H
H
H
L
X
X
X
X
Not Selected
Read SRAM
Write SRAM
Active
Active
l
n
L
X
X
Nonvolatile STORE
Output High Z
m
CC
2
Note m: HSB STORE operation occurs only if an SRAM write has been done since the last nonvolatile cycle. After the STORE (if any) completes, the
part will go into standby mode, inhibiting all operations until HSB rises.
Note n: I/O state assumes G < VIL. Activation of nonvolatile cycles does not depend on state of G.
e
HARDWARE STORE CYCLE
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK22C48
PARAMETER
UNITS NOTES
Standard
Alternate
MIN
1
MAX
22
23
24
25
26
t
t
t
t
t
t
t
t
STORE Cycle Duration
10
ms
μs
ns
ns
ns
i, o
i, p
STORE
DELAY
RECOVER
HLHX
HLHZ
HLQZ
HHQX
Time Allowed to Complete SRAM Cycle
Hardware STORE High to Inhibit Off
Hardware STORE Pulse Width
700
300
o, q
15
Hardware STORE Low to Store Busy
HLBL
Note o: E and G low for output behavior.
Note p: E and G low and W high for output behavior.
Note q: tRECOVER is only applicable after tSTORE is complete.
HARDWARE STORE CYCLE
25
HLHX
t
HSB (IN)
24
RECOVER
t
22
STORE
t
26
HLBL
t
HSB (OUT)
HIGH IMPEDANCE
HIGH IMPEDANCE
DATA VALID
23
DELAY
t
DQ (DATA OUT)
DATA VALID
Rev 0.3
Document Control #ML0004
February 2007
6
SIMTEK [ SIMTEK CORPORATION ]
