STK22C48
PIN CONFIGURATIONS
1
VCAP
NC
A7
A6
A5
A4
A3
A2
A1
28
27
26
25
24
23
22
21
20
VCCX
W
HSB
A8
A9
NC
G
A10
E
2
3
4
5
6
7
8
9
10
11
12
13
14
19
18
17
16
15
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
VSS
28-pin 300 mil SOIC
28-pin 330 mil SOIC
PIN NAMES
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 11 address inputs select one of 2,048 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
10
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
V
Power Supply
Power Supply
Power: 5.0V, ±10%
Ground
CC
SS
Rev 0.3
Document Control #ML0004
February 2007
2
SIMTEK [ SIMTEK CORPORATION ]
