STK22C48
SRAM READ CYCLES #1 & #2
e
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK22C48-25
STK22C48-45
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
25
45
AVAV
h
3
Address Access Time
Output Enable to Data Valid
25
10
45
20
AVQV
4
GLQV
OE
OH
LZ
h
5
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
5
5
5
5
AXQX
6
ELQX
i
7
10
10
25
15
15
45
EHQZ
HZ
8
0
0
0
0
GLQX
OLZ
OHZ
PA
i
9
GHQZ
f
f
10
11
ELICCH
EHICCL
PS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured 200mV from steady state output voltage.
g, h
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
g
SRAM READ CYCLE #2: E Controlled
2
t
AVAV
ADDRESS
E
1
11
EHICCL
t
ELQV
t
6
t
ELQX
7
t
EHQZ
G
9
t
4
GHQZ
t
GLQV
8
t
GLQX
DQ (DATA OUT)
DATA VALID
10
ELICCH
t
ACTIVE
STANDBY
I
CC
e
SRAM WRITE CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK22C48-25 STK22C48-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
MAX
MIN
45
MAX
12
13
t
t
t
WC
Write Cycle Time
Write Pulse Width
ns
ns
AVAV
AVAV
t
t
t
WP
20
30
WLWH
WLEH
Rev 0.3
Document Control #ML0004
February 2007
4