STK16CA8
SRAM READ CYCLES #1 & #2
(VCC = 3.0V +20%, -10%)
SYMBOLS
STK16CA8-25
STK16CA8-35
STK16CA8-45
NO.
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
f
Read Cycle Time
25
35
45
AVAV
g
3
Address Access Time
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
g
5
3
3
3
3
3
3
AXQX
6
ELQX
h
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
e
10
11
ELICCH
EHICCL
PS
Note f: W must be high during SRAM READ cycles.
Note g: Device is continuously selected with E and G both low.
Note h: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
2
t
AVAV
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E Controlledf
2
t
AVAV
ADDRESS
E
1
11
t
ELQV
t
EHICCL
6
t
ELQX
7
t
EHQZ
G
9
4
t
GHQZ
t
GLQV
8
t
GLQX
DATA VALID
DQ (DATA OUT)
10
t
ELICCH
ACTIVE
STANDBY
I
CC
September 2003
3
Document Control # ML0023 rev 0.1
SIMTEK [ SIMTEK CORPORATION ]
