SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Serial ATA SError
Address Offset: 108H / 188H / 308H / 388H
Access Type: Read/Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
F
T
S
H
C
D
B
W
I
N
E
P
C
T
M
I
DIAG
ERR
This register is the SError register as defined by the Serial ATA specification (section 10.1.2).
• Bit [31:16]: DIAG – This field contains bits defined as shown in the following table. Writing a 1 to the
register bit clears the B, C, F, N, H, and W bits.
Table 25. SError Register Bits (DIAG Field)
Bit
B
Definition
Description
10b to 8b decode error
CRC error
Latched decode error or disparity error from the Serial ATA PHY
Latched CRC error from the Serial ATA PHY
C
D
Disparity error
N/A, always 0; this error condition is combined with the decode error and
reported as B error
F
I
Unrecognized FIS type
PHY Internal error
PHYRDY change
Handshake error
Reserved
Latched Unrecognized FIS error from the Serial ATA Link
N/A, always 0
N
H
R
S
T
Indicates a change in the status of the Serial ATA PHY
Latched Handshake error from the Serial ATA PHY
Always 0
Link Sequence error
Transport state transition error
ComWake
N/A, always 0
N/A, always 0
W
Latched ComWake status from the Serial ATA PHY
• Bit [15:00]: ERR – This field contains bits defined as shown in the following table. The ERR Field is not
implemented; all bits are always 0.
Table 26. SError Register Bits (ERR Field)
Bit
C
E
I
Definition
Description
N/A, always 0
N/A, always 0
N/A, always 0
N/A, always 0
N/A, always 0
Always 0
Non-recovered persistent Communication error or data integrity error
Internal Error
Recovered data Integrity error
Recovered communications error
Protocol error
M
P
R
T
Reserved
Non-recovered Transient data integrity error
N/A, always 0
© 2007 Silicon Image, Inc.
69
SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
