SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Serial ATA SStatus
Address Offset: 104H / 184H / 304H / 384H
Access Type: Read
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
IPM
SPD
DET
This register is the SStatus register as defined by the Serial ATA specification (section 10.1.1).
• Bit [31:12]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [11:08]: IPM – This field identifies the current interface power management state.
Value
0000
0001
0010
0110
others
Definition
Device not present or communication not established
Interface in active state
Interface in Partial power management state
Interface in Slumber power management state
Reserved
• Bit [07:04]: SPD – This field identifies the negotiated interface communication speed.
Value
Definition
0000
No negotiated speed
0001
Generation 1 communication rate (1.5 Gbit/s)
Reserved
others
• Bit [03:00]: DET – This field indicates the interface device detection and PHY state.
Value
0000
0001
0011
0100
Action
No device detected and PHY communication not established
Device presence detected but PHY communication not established
Device presence detected and PHY communication established
PHY in offline mode as a result of the interface being disabled or running in a BIST loopback
mode
others
Reserved, no action
Until a device is detected (IPM and DET fields become nonzero), the SiI3114 issues a COMRESET every 100
milliseconds.
SiI-DS-0103-D
68
© 2007 Silicon Image, Inc.
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