SiI 1161 PanelLink Receiver
Data Sheet
Table 12. Two Pixels per Clock Input/Output TFT Mode
TFT VGA Output
Tx Input Data
160
Rx Output Data
1161
TFT Panel Input
24-bpp
B0 – 0
B1 – 0
B2 – 0
B3 – 0
B4 – 0
B5 – 0
B6 – 0
B7 – 0
G0 – 0
G1 – 0
G2 – 0
G3 – 0
G4 – 0
G5 – 0
G6 – 0
G7 – 0
R0 – 0
R1 – 0
R2 – 0
R3 – 0
R4 – 0
R5 – 0
R6 – 0
R7 – 0
B0 – 1
B1 – 1
B2 – 1
B3 – 1
B4 – 1
B5 – 1
B6 – 1
B7 – 1
G0 – 1
G1 – 1
G2 – 1
G3 – 1
G4 – 1
G5 – 1
G6 – 1
G7 – 1
R0 – 1
R1 – 1
R2 – 1
R3 – 1
R4 – 1
R5 – 1
R6 – 1
R7 – 1
18-bpp
24-bpp
B0 – 0
B1 – 0
B2 – 0
B3 – 0
B4 – 0
B5 – 0
B6 – 0
B7 – 0
G0 – 0
G1 – 0
G2 – 0
G3 – 0
G4 – 0
G5 – 0
G6 – 0
G7 – 0
R0 – 0
R1 – 0
R2 – 0
R3 – 0
R4 – 0
R5 – 0
R6 – 0
R7 – 0
B0 – 1
B1 – 1
B2 – 1
B3 – 1
B4 – 1
B5 – 1
B6 – 1
B7 – 1
G0 – 1
G1 – 1
G2 – 1
G3 – 1
G4 – 1
G5 – 1
G6 – 1
G7 – 1
R0 – 1
R1 – 1
R2 – 1
R3 – 1
R4 – 1
R5 – 1
R6 – 1
R7 – 1
Shift CLK
VSYNC
HSYNC
DE
18-bpp
DIE0
DIE1
DIE2
DIE3
DIE4
DIE5
DIE6
DIE7
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
B0 – 0
B1 – 0
B2 – 0
B3 – 0
B4 – 0
B5 – 0
B0 – 0
B1 – 0
B2 – 0
B3 – 0
B4 – 0
B5 – 0
DIE8
DIE9
QE8
QE9
G0 – 0
G1 – 0
G2 – 0
G3 – 0
G4 – 0
G5 – 0
DIE10
DIE11
DIE12
DIE13
DIE14
DIE15
DIE16
DIE17
DIE18
DIE19
DIE20
DIE21
DIE22
DIE23
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
DIO6
DIO7
QE10
QE11
QE12
QE13
QE14
QE15
QE16
QE17
QE18
QE19
QE20
QE21
QE22
QE23
QO0
QO1
QO2
QO3
QO4
QO5
QO6
QO7
G0 – 0
G1 – 0
G2 – 0
G3 – 0
G4 – 0
G5 – 0
R0 – 0
R1 – 0
R2 – 0
R3 – 0
R4 – 0
R5 – 0
R0 – 0
R1 – 0
R2 – 0
R3 – 0
R4 – 0
R5 – 0
B0 – 1
B1 – 1
B2 – 1
B3 – 1
B4 – 1
B5 – 1
B0 – 1
B1 – 1
B2 – 1
B3 – 1
B4 – 1
B5 – 1
DIO8
DIO9
QO8
QO9
G0 – 1
G1 – 1
G2 – 1
G3 – 1
G4 – 1
G5 – 1
DIO10
DIO11
DIO12
DIO13
DIO14
DIO15
DIO16
DIO17
DIO18
DIO19
DIO20
DIO21
DIO22
DIO23
IDCK
VSYNC
HSYNC
DE
QO10
QO11
QO12
QO13
QO14
QO15
QO16
QO17
QO18
QO19
QO20
QO21
QO22
QO23
ODCK
VSYNC
HSYNC
DE
G0 – 1
G1 – 1
G2 – 1
G3 – 1
G4 – 1
G5 – 1
R0 – 1
R1 – 1
R2 – 1
R3 – 1
R4 – 1
R5 – 1
R0 – 1
R1 – 1
R2 – 1
R3 – 1
R4 – 1
R5 – 1
Shift CLK
VSYNC
HSYNC
DE
ShiftClk/2 ShiftClk/2
VSYNC
HSYNC
DE
VSYNC
HSYNC
DE
SiI-DS-0096-D
26
SILICONIMAGE [ Silicon image ]
