SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.27 IDE0 Task File Register 2
Address Offset: 88H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
IDE0 Task File Device Control
IDE0 Task File Auxiliary Status
Reserved
Reserved
This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. Access to these bit fields is permitted if
the PCI bus Byte Enable is active for one byte only.
The register bits are defined below.
•
•
•
Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [23:16]: IDE0 Task File Device Control (W). This bit field defines the IDE0 Task File Device Control register.
Bit [23:16]: IDE0 Task File Auxiliary Status (R). This bit field defines the IDE0 Task File Auxiliary Status
register.
•
Bit [15:00]: Reserved (R). This bit field is reserved and returns zeros on a read.
9.7.28 IDE0 Read Ahead Data
Address Offset: 8CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE0 Read Ahead Data
This register defines the read ahead data port for PIO transfers on IDE Channel #0 in the SiI 0680A. This register can be
accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to this register must
be zero-aligned.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
86
SILICONIMAGE [ Silicon image ]
