SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.31 IDE0 UDMA Control
Address Offset: 98H
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
•
This bit field is reserved and returns an indeterminate value on a read.
9.7.32 IDE0 Virtual DMA/PIO Read Ahead Byte Count
Address Offset: 9CH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE0 Virtual DMA/PIO Read Ahead Byte Count
This register defines the read ahead byte count register for Virtual DMA and PIO Read Ahead transfers on IDE Channel #0 in
the SiI 0680A. In Virtual DMA mode (PCI bus master DMA with PIO transfers on the IDE), all 32 bits are used as the word-
aligned byte count. In PIO Read Ahead mode, only the lower 16 bits are used as the word-aligned byte count. The higher 16
bits must be programmed 0x0000.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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